1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7class IssueQueue(val fuTypeInt: BigInt, wakeupCnt: Int, val bypassCnt: Int) extends XSModule with NeedImpl { 8 9 val useBypass = bypassCnt > 0 10 11 val io = IO(new Bundle() { 12 // flush Issue Queue 13 val redirect = Flipped(ValidIO(new Redirect)) 14 15 // enq Ctrl sigs at dispatch-2 16 val enqCtrl = Flipped(DecoupledIO(new MicroOp)) 17 // enq Data at next cycle (regfile has 1 cycle latency) 18 val enqData = Flipped(ValidIO(new ExuInput)) 19 20 val deq = DecoupledIO(new ExuInput) 21 val wakeUpPorts = Vec(wakeupCnt, Flipped(DecoupledIO(new ExuOutput))) 22 val bypassPorts = if(useBypass) Vec(bypassCnt, Flipped(DecoupledIO(new ExuOutput))) else null 23 }) 24} 25