xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision ac4d321d18df4775b9ddda83e77cf526a0b1ca67) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne, GatedValidRegNext}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19
20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
21  override def shouldBeInlined: Boolean = false
22
23  implicit val iqParams = params
24  lazy val module: IssueQueueImp = iqParams.schdType match {
25    case IntScheduler() => new IssueQueueIntImp(this)
26    case VfScheduler() => new IssueQueueVfImp(this)
27    case MemScheduler() =>
28      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
29      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
30      else new IssueQueueIntImp(this)
31    case _ => null
32  }
33}
34
35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
36  val empty = Output(Bool())
37  val full = Output(Bool())
38  val validCnt = Output(UInt(log2Ceil(numEntries).W))
39  val leftVec = Output(Vec(numEnq + 1, Bool()))
40}
41
42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
43
44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
45  // Inputs
46  val flush = Flipped(ValidIO(new Redirect))
47  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
48
49  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
54  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
55  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
56  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
57  val og0Cancel = Input(ExuOH(backendParams.numExu))
58  val og1Cancel = Input(ExuOH(backendParams.numExu))
59  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
65  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
66
67  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
68  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
69}
70
71class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
72  extends LazyModuleImp(wrapper)
73  with HasXSParameter {
74
75  override def desiredName: String = s"${params.getIQName}"
76
77  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
78    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
79    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
80    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
81    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
82    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
83
84  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
85  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
86  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
87  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
88
89  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
90  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
91  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
92  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
93  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
94
95  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
96  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
97  lazy val io = IO(new IssueQueueIO())
98
99  // Modules
100  val entries = Module(new Entries)
101  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
102  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
103  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
104  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
105  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
106  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
107
108  class WakeupQueueFlush extends Bundle {
109    val redirect = ValidIO(new Redirect)
110    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
111    val og0Fail = Output(Bool())
112    val og1Fail = Output(Bool())
113  }
114
115  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
116    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
117    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
118    val ogFailFlush = stage match {
119      case 1 => flush.og0Fail
120      case 2 => flush.og1Fail
121      case _ => false.B
122    }
123    redirectFlush || loadDependencyFlush || ogFailFlush
124  }
125
126  private def modificationFunc(exuInput: ExuInput): ExuInput = {
127    val newExuInput = WireDefault(exuInput)
128    newExuInput.loadDependency match {
129      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
130      case None =>
131    }
132    newExuInput
133  }
134
135  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
136    val lastExuInput = WireDefault(exuInput)
137    val newExuInput = WireDefault(newInput)
138    newExuInput.elements.foreach { case (name, data) =>
139      if (lastExuInput.elements.contains(name)) {
140        data := lastExuInput.elements(name)
141      }
142    }
143    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
144      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
145    }
146    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
147      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
148    }
149    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
150      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
151    }
152    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
153      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
154    }
155    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
156      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
157    }
158    newExuInput
159  }
160
161  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
162    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
163  ))}
164  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
165
166  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
167  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
168  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
169  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
170  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
171  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
172  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
173  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
174  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
175  val s0_enqValidVec = io.enq.map(_.valid)
176  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
177  val s0_enqNotFlush = !io.flush.valid
178  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
179  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
180
181
182  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
183  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
184
185  val validVec = VecInit(entries.io.valid.asBools)
186  val canIssueVec = VecInit(entries.io.canIssue.asBools)
187  dontTouch(canIssueVec)
188  val deqFirstIssueVec = entries.io.isFirstIssue
189
190  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
191  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
192  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
193  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
194  // (entryIdx)(srcIdx)(exuIdx)
195  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
196  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
197
198  // (deqIdx)(srcIdx)(exuIdx)
199  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
200  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
201
202  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
203  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
204  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
205  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
206
207  //deq
208  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
209  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
210  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
211  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
212  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
213  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
214  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
215
216  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
217  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
218  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
219
220  //trans
221  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
222  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
223  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
224  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
225  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
226
227  /**
228    * Connection of [[entries]]
229    */
230  entries.io match { case entriesIO: EntriesIO =>
231    entriesIO.flush                                             := io.flush
232    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
233      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
234      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
235      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
236      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
237      for(j <- 0 until numLsrc) {
238        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
239        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
240        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
241        enq.bits.status.srcStatus(j).dataSources.value          := Mux(
242          SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
243          DataSource.zero,
244          Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg)
245        )
246        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1))
247        if(params.hasIQWakeUp) {
248          enq.bits.status.srcStatus(j).srcTimer.get             := 0.U(3.W)
249          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
250        }
251      }
252      enq.bits.status.blocked                                   := false.B
253      enq.bits.status.issued                                    := false.B
254      enq.bits.status.firstIssue                                := false.B
255      enq.bits.status.issueTimer                                := "b10".U
256      enq.bits.status.deqPortIdx                                := 0.U
257      enq.bits.imm.foreach(_                                    := s0_enqBits(enqIdx).imm)
258      enq.bits.payload                                          := s0_enqBits(enqIdx)
259    }
260    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
261      og0Resp                                                   := io.og0Resp(i)
262    }
263    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
264      og1Resp                                                   := io.og1Resp(i)
265    }
266    if (params.isLdAddrIQ || params.isHyAddrIQ) {
267      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
268        finalIssueResp                                          := io.finalIssueResp.get(i)
269      }
270      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
271        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
272      }
273    }
274    for(deqIdx <- 0 until params.numDeq) {
275      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
276      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
277      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
278      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
279      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
280      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
281      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
282      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
283      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
284    }
285    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
286    entriesIO.wakeUpFromIQ                                      := io.wakeupFromIQ
287    entriesIO.og0Cancel                                         := io.og0Cancel
288    entriesIO.og1Cancel                                         := io.og1Cancel
289    entriesIO.ldCancel                                          := io.ldCancel
290    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
291    //output
292    fuTypeVec                                                   := entriesIO.fuType
293    deqEntryVec                                                 := entriesIO.deqEntry
294    cancelDeqVec                                                := entriesIO.cancelDeqVec
295    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
296    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
297    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
298  }
299
300
301  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
302
303  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
304    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
305  ).reverse)
306
307  // if deq port can accept the uop
308  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
309    Cat(fuTypeVec.map(fuType =>
310      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
311    ).reverse)
312  }
313
314  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
315    fuTypeVec.map(fuType =>
316      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
317  }
318
319  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
320    val mergeFuBusy = {
321      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
322      else canIssueVec.asUInt
323    }
324    val mergeIntWbBusy = {
325      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
326      else mergeFuBusy
327    }
328    val mergeVfWbBusy = {
329      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
330      else mergeIntWbBusy
331    }
332    merge := mergeVfWbBusy
333  }
334
335  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
336    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
337  }
338  dontTouch(fuTypeVec)
339  dontTouch(canIssueMergeAllBusy)
340  dontTouch(deqCanIssue)
341
342  if (params.numDeq == 2) {
343    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
344  }
345
346  if (params.numDeq == 2 && params.deqFuSame) {
347    val subDeqPolicy = Module(new DeqPolicy())
348
349    enqEntryOldestSel := DontCare
350
351    if (params.isAllComp || params.isAllSimp) {
352      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
353        enq = othersEntryEnqSelVec.get,
354        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
355      )
356      othersEntryOldestSel(1) := DontCare
357
358      subDeqPolicy.io.request := subDeqRequest.get
359      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
360      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
361    }
362    else {
363      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
364      simpAgeDetectRequest.get(1) := DontCare
365      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
366      if (params.numEnq == 2) {
367        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
368      }
369
370      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
371        enq = simpEntryEnqSelVec.get,
372        canIssue = simpAgeDetectRequest.get
373      )
374
375      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
376        enq = compEntryEnqSelVec.get,
377        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
378      )
379      compEntryOldestSel.get(1) := DontCare
380
381      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
382      othersEntryOldestSel(0).bits := Cat(
383        compEntryOldestSel.get(0).bits,
384        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
385      )
386      othersEntryOldestSel(1) := DontCare
387
388      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
389      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
390      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
391    }
392
393    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
394
395    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
396    deqSelValidVec(1) := subDeqSelValidVec.get(0)
397    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
398                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
399                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
400    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
401
402    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
403      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
404      selOH := deqOH
405    }
406  }
407  else {
408    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
409      enq = VecInit(s0_doEnqSelValidVec),
410      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
411    )
412
413    if (params.isAllComp || params.isAllSimp) {
414      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
415        enq = othersEntryEnqSelVec.get,
416        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
417      )
418
419      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
420        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
421          selValid := false.B
422          selOH := 0.U.asTypeOf(selOH)
423        } else {
424          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
425          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
426        }
427      }
428    }
429    else {
430      othersEntryOldestSel := DontCare
431
432      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
433        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
434      }
435      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
436      if (params.numEnq == 2) {
437        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
438      }
439
440      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
441        enq = simpEntryEnqSelVec.get,
442        canIssue = simpAgeDetectRequest.get
443      )
444
445      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
446        enq = compEntryEnqSelVec.get,
447        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
448      )
449
450      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
451        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
452          selValid := false.B
453          selOH := 0.U.asTypeOf(selOH)
454        } else {
455          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
456          selOH := Cat(
457            compEntryOldestSel.get(i).bits,
458            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
459            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
460          )
461        }
462      }
463    }
464
465    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
466      selValid := deqValid && deqBeforeDly(i).ready
467      selOH := deqOH
468    }
469  }
470
471  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
472
473  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
474    deqResp.valid := finalDeqSelValidVec(i)
475    deqResp.bits.resp   := RespType.success
476    deqResp.bits.robIdx := DontCare
477    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
478    deqResp.bits.uopIdx.foreach(_ := DontCare)
479  }
480
481  //fuBusyTable
482  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
483    if(busyTableWrite.nonEmpty) {
484      val btwr = busyTableWrite.get
485      val btrd = busyTableRead.get
486      btwr.io.in.deqResp := toBusyTableDeqResp(i)
487      btwr.io.in.og0Resp := io.og0Resp(i)
488      btwr.io.in.og1Resp := io.og1Resp(i)
489      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
490      btrd.io.in.fuTypeRegVec := fuTypeVec
491      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
492    }
493    else {
494      fuBusyTableMask(i) := 0.U(params.numEntries.W)
495    }
496  }
497
498  //wbfuBusyTable write
499  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
500    if(busyTableWrite.nonEmpty) {
501      val btwr = busyTableWrite.get
502      val bt = busyTable.get
503      val dq = deqResp.get
504      btwr.io.in.deqResp := toBusyTableDeqResp(i)
505      btwr.io.in.og0Resp := io.og0Resp(i)
506      btwr.io.in.og1Resp := io.og1Resp(i)
507      bt := btwr.io.out.fuBusyTable
508      dq := btwr.io.out.deqRespSet
509    }
510  }
511
512  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
513    if (busyTableWrite.nonEmpty) {
514      val btwr = busyTableWrite.get
515      val bt = busyTable.get
516      val dq = deqResp.get
517      btwr.io.in.deqResp := toBusyTableDeqResp(i)
518      btwr.io.in.og0Resp := io.og0Resp(i)
519      btwr.io.in.og1Resp := io.og1Resp(i)
520      bt := btwr.io.out.fuBusyTable
521      dq := btwr.io.out.deqRespSet
522    }
523  }
524
525  //wbfuBusyTable read
526  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
527    if(busyTableRead.nonEmpty) {
528      val btrd = busyTableRead.get
529      val bt = busyTable.get
530      btrd.io.in.fuBusyTable := bt
531      btrd.io.in.fuTypeRegVec := fuTypeVec
532      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
533    }
534    else {
535      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
536    }
537  }
538  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
539    if (busyTableRead.nonEmpty) {
540      val btrd = busyTableRead.get
541      val bt = busyTable.get
542      btrd.io.in.fuBusyTable := bt
543      btrd.io.in.fuTypeRegVec := fuTypeVec
544      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
545    }
546    else {
547      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
548    }
549  }
550
551  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
552    wakeUpQueueOption.foreach {
553      wakeUpQueue =>
554        val flush = Wire(new WakeupQueueFlush)
555        flush.redirect := io.flush
556        flush.ldCancel := io.ldCancel
557        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
558        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
559        wakeUpQueue.io.flush := flush
560        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
561        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
562        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
563        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
564    }
565  }
566
567  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
568    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
569    deq.bits.addrOH          := finalDeqSelOHVec(i)
570    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
571    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
572    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
573    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
574    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
575    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
576    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
577    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
578    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
579    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
580
581    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
582    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
583    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
584    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
585    deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i))
586    deq.bits.common.src := DontCare
587    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
588
589    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
590      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
591      rf.foreach(_.addr := psrc)
592      rf.foreach(_.srcType := srcType)
593    }
594    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
595      sink := source
596    }
597    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
598    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
599
600    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
601    deq.bits.common.perfDebugInfo.selectTime := GTimer()
602    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
603  }
604
605  private val deqShift = WireDefault(deqBeforeDly)
606  deqShift.zip(deqBeforeDly).foreach {
607    case (shifted, original) =>
608      original.ready := shifted.ready // this will not cause combinational loop
609      shifted.bits.common.loadDependency.foreach(
610        _ := original.bits.common.loadDependency.get.map(_ << 1)
611      )
612  }
613  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
614    NewPipelineConnect(
615      deq, deqDly, deqDly.valid,
616      false.B,
617      Option("Scheduler2DataPathPipe")
618    )
619  }
620  if(backendParams.debugEn) {
621    dontTouch(io.deqDelay)
622  }
623  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
624    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
625      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
626      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
627      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
628      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
629    } else if (wakeUpQueues(i).nonEmpty) {
630      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
631      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
632      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
633      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
634    } else {
635      wakeup.valid := false.B
636      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
637      wakeup.bits.is0Lat :=  0.U
638    }
639    if (wakeUpQueues(i).nonEmpty) {
640      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
641      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
642      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
643    }
644
645    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
646      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
647    }
648    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
649      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
650    }
651    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
652      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
653    }
654    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
655      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
656    }
657    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
658      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
659    }
660  }
661
662  // Todo: better counter implementation
663  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
664  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
665  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
666  private val enqEntryValidCntDeq0 = PopCount(
667    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
668  )
669  private val othersValidCntDeq0 = PopCount(
670    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
671  )
672  private val enqEntryValidCntDeq1 = PopCount(
673    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
674  )
675  private val othersValidCntDeq1 = PopCount(
676    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
677  )
678  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
679    io.enq.map(_.bits.fuType).map(fuType =>
680      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
681  }
682  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
683  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
684  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
685  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
686  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
687  for (i <- 0 until params.numEnq) {
688    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
689  }
690  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
691  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
692    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
693  }
694  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
695  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
696
697  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
698  io.status.empty := !Cat(validVec).orR
699  io.status.full := othersCanotIn
700  io.status.validCnt := PopCount(validVec)
701
702  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
703    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
704  }
705
706  // issue perf counter
707  // enq count
708  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
709  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
710  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
711  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
712  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
713  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
714  // valid count
715  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
716  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
717  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
718  // only split when more than 1 func type
719  if (params.getFuCfgs.size > 0) {
720    for (t <- FuType.functionNameMap.keys) {
721      val fuName = FuType.functionNameMap(t)
722      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
723        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
724      }
725    }
726  }
727  // ready instr count
728  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
729  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
730  // only split when more than 1 func type
731  if (params.getFuCfgs.size > 0) {
732    for (t <- FuType.functionNameMap.keys) {
733      val fuName = FuType.functionNameMap(t)
734      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
735        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
736      }
737    }
738  }
739
740  // deq instr count
741  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
742  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
743  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
744  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
745
746  // deq instr data source count
747  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
748    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
749  }.reduce(_ +& _))
750  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
751    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
752  }.reduce(_ +& _))
753  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
754    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
755  }.reduce(_ +& _))
756  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
757    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
758  }.reduce(_ +& _))
759
760  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
761    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
762  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
763  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
764    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
765  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
766  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
767    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
768  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
769  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
770    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
771  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
772
773  // deq instr data source count for each futype
774  for (t <- FuType.functionNameMap.keys) {
775    val fuName = FuType.functionNameMap(t)
776    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
777      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
778        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
779      }.reduce(_ +& _))
780      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
781        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
782      }.reduce(_ +& _))
783      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
784        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
785      }.reduce(_ +& _))
786      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
787        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
788      }.reduce(_ +& _))
789
790      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
791        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
792      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
793      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
794        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
795      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
796      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
797        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
798      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
799      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
800        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
801      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
802    }
803  }
804
805  // cancel instr count
806  if (params.hasIQWakeUp) {
807    val cancelVec: Vec[Bool] = entries.io.cancel.get
808    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
809    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
810    for (t <- FuType.functionNameMap.keys) {
811      val fuName = FuType.functionNameMap(t)
812      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
813        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
814        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
815      }
816    }
817  }
818}
819
820class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
821  val fastMatch = UInt(backendParams.LduCnt.W)
822  val fastImm = UInt(12.W)
823}
824
825class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
826
827class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
828  extends IssueQueueImp(wrapper)
829{
830  io.suggestName("none")
831  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
832
833  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
834    deq.bits.common.pc.foreach(_ := DontCare)
835    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
836    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
837    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
838    deq.bits.common.predictInfo.foreach(x => {
839      x.target := DontCare
840      x.taken := deqEntryVec(i).bits.payload.pred_taken
841    })
842    // for std
843    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
844    // for i2f
845    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
846  }}
847}
848
849class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
850  extends IssueQueueImp(wrapper)
851{
852  s0_enqBits.foreach{ x =>
853    x.srcType(3) := SrcType.vp // v0: mask src
854    x.srcType(4) := SrcType.vp // vl&vtype
855  }
856  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
857    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
858    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
859    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
860    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
861  }}
862}
863
864class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
865  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
866
867  // TODO: is still needed?
868  val checkWait = new Bundle {
869    val stIssuePtr = Input(new SqPtr)
870    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
871  }
872  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
873
874  // load wakeup
875  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
876
877  // vector
878  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
879  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
880}
881
882class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
883  val memIO = Some(new IssueQueueMemBundle)
884}
885
886class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
887  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
888
889  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
890    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
891  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
892
893  io.suggestName("none")
894  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
895  private val memIO = io.memIO.get
896
897  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
898
899  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
900    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
901    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
902    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
903    slowResp.bits.fuType := DontCare
904  }
905
906  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
907    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
908    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
909    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
910    fastResp.bits.fuType := DontCare
911  }
912
913  // load wakeup
914  val loadWakeUpIter = memIO.loadWakeUp.iterator
915  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
916    if (param.hasLoadExu) {
917      require(wakeUpQueues(i).isEmpty)
918      val uop = loadWakeUpIter.next()
919
920      wakeup.valid := GatedValidRegNext(uop.fire)
921      wakeup.bits.rfWen  := GatedValidRegNext(uop.bits.rfWen  && uop.fire)
922      wakeup.bits.fpWen  := GatedValidRegNext(uop.bits.fpWen  && uop.fire)
923      wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire)
924      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
925      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
926
927      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen  && uop.fire)))
928      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen  && uop.fire)))
929      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire)))
930      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
931      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
932
933      wakeup.bits.is0Lat := 0.U
934    }
935  }
936  require(!loadWakeUpIter.hasNext)
937
938  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
939    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
940    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
941    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
942    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
943    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
944    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
945    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
946    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
947    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
948  }
949}
950
951class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
952  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
953
954  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
955  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
956
957  io.suggestName("none")
958  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
959  private val memIO = io.memIO.get
960
961  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
962
963  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
964    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
965    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
966      (if (j < i) !valid(j) || compareVec(i)(j)
967      else if (j == i) valid(i)
968      else !valid(j) || !compareVec(j)(i))
969    )).andR))
970    resultOnehot
971  }
972
973  val robIdxVec = entries.io.robIdx.get
974  val uopIdxVec = entries.io.uopIdx.get
975  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
976
977  deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
978  deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
979  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready
980  finalDeqSelOHVec.head := deqSelOHVec.head
981
982  s0_enqBits.foreach{ x =>
983    x.srcType(3) := SrcType.vp // v0: mask src
984    x.srcType(4) := SrcType.vp // vl&vtype
985  }
986
987  for (i <- entries.io.enq.indices) {
988    entries.io.enq(i).bits.status match { case enqData =>
989      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
990      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
991
992      // update blocked
993      val isLsqHead = {
994        s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get &&
995        s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get
996      }
997      enqData.blocked          := !isLsqHead
998    }
999  }
1000
1001  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1002    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1003    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1004    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1005    slowResp.bits.fuType           := DontCare
1006    slowResp.bits.uopIdx.get       := 0.U // Todo
1007  }
1008
1009  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1010    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1011    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1012    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1013    fastResp.bits.fuType           := DontCare
1014    fastResp.bits.uopIdx.get       := 0.U // Todo
1015  }
1016
1017  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1018  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1019
1020
1021  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1022    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1023    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1024    if (params.isVecLduIQ) {
1025      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1026      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1027    }
1028    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1029    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1030    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1031    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1032  }
1033}
1034