1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19import xiangshan.backend.fu.vector.Bundles.VSew 20 21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 override def shouldBeInlined: Boolean = false 23 24 implicit val iqParams = params 25 lazy val module: IssueQueueImp = iqParams.schdType match { 26 case IntScheduler() => new IssueQueueIntImp(this) 27 case FpScheduler() => new IssueQueueFpImp(this) 28 case VfScheduler() => new IssueQueueVfImp(this) 29 case MemScheduler() => 30 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 31 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 32 else new IssueQueueIntImp(this) 33 case _ => null 34 } 35} 36 37class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 38 val empty = Output(Bool()) 39 val full = Output(Bool()) 40 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 41 val leftVec = Output(Vec(numEnq + 1, Bool())) 42} 43 44class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 45 46class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 47 // Inputs 48 val flush = Flipped(ValidIO(new Redirect)) 49 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 50 51 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 53 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 57 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 58 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 59 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 60 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 61 val vlIsZero = Input(Bool()) 62 val vlIsVlmax = Input(Bool()) 63 val og0Cancel = Input(ExuOH(backendParams.numExu)) 64 val og1Cancel = Input(ExuOH(backendParams.numExu)) 65 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 66 67 // Outputs 68 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 69 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 70 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 71 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 72 73 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 74 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 75} 76 77class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 78 extends LazyModuleImp(wrapper) 79 with HasXSParameter { 80 81 override def desiredName: String = s"${params.getIQName}" 82 83 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 84 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 85 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 86 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 87 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 88 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 89 90 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 91 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 92 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 93 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 94 95 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 96 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 97 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 98 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 99 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 100 101 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 102 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 103 lazy val io = IO(new IssueQueueIO()) 104 105 // Modules 106 val entries = Module(new Entries) 107 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 108 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 109 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 110 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 111 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 112 val fpWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 113 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 114 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 115 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.v0LatencyCertain, Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 116 val v0WbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.v0LatencyCertain, Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 117 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vlLatencyCertain, Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 118 val vlWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vlLatencyCertain, Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 119 120 class WakeupQueueFlush extends Bundle { 121 val redirect = ValidIO(new Redirect) 122 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 123 val og0Fail = Output(Bool()) 124 val og1Fail = Output(Bool()) 125 } 126 127 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 128 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 129 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 130 val ogFailFlush = stage match { 131 case 1 => flush.og0Fail 132 case 2 => flush.og1Fail 133 case _ => false.B 134 } 135 redirectFlush || loadDependencyFlush || ogFailFlush 136 } 137 138 private def modificationFunc(exuInput: ExuInput): ExuInput = { 139 val newExuInput = WireDefault(exuInput) 140 newExuInput.loadDependency match { 141 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 142 case None => 143 } 144 newExuInput 145 } 146 147 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 148 val lastExuInput = WireDefault(exuInput) 149 val newExuInput = WireDefault(newInput) 150 newExuInput.elements.foreach { case (name, data) => 151 if (lastExuInput.elements.contains(name)) { 152 data := lastExuInput.elements(name) 153 } 154 } 155 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 156 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 157 } 158 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 159 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 160 } 161 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 162 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 163 } 164 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 165 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 166 } 167 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 168 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 169 } 170 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 171 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 172 } 173 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 174 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 175 } 176 newExuInput 177 } 178 179 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 180 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 181 ))} 182 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 183 184 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 185 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 186 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 187 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 188 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 189 190 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 191 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 192 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 193 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 194 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 195 196 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 197 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 198 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 199 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 200 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 201 202 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 203 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 209 val s0_enqValidVec = io.enq.map(_.valid) 210 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 211 val s0_enqNotFlush = !io.flush.valid 212 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 213 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 214 215 216 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 217 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 218 219 val validVec = VecInit(entries.io.valid.asBools) 220 val canIssueVec = VecInit(entries.io.canIssue.asBools) 221 dontTouch(canIssueVec) 222 val deqFirstIssueVec = entries.io.isFirstIssue 223 224 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 225 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 226 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 227 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 228 // (entryIdx)(srcIdx)(exuIdx) 229 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 230 // (deqIdx)(srcIdx)(exuIdx) 231 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 232 233 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 234 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 235 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 236 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 237 238 //deq 239 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 240 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 241 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 242 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 243 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 244 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 245 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 246 247 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 248 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 249 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 250 251 //trans 252 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 253 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 254 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 255 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 256 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 257 258 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 259 // as vf exu's min latency is 1, we do not need consider og0cancel 260 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 261 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 262 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 263 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 264 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 265 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 266 } else { 267 w := w_src 268 } 269 } 270 271 /** 272 * Connection of [[entries]] 273 */ 274 entries.io match { case entriesIO: EntriesIO => 275 entriesIO.flush := io.flush 276 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 277 enq.valid := s0_doEnqSelValidVec(enqIdx) 278 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 279 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 280 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 281 for(j <- 0 until numLsrc) { 282 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 283 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 284 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 285 enq.bits.status.srcStatus(j).dataSources.value := Mux( 286 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 287 DataSource.zero, 288 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 289 ) 290 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 291 if(params.hasIQWakeUp) { 292 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 293 } 294 } 295 enq.bits.status.blocked := false.B 296 enq.bits.status.issued := false.B 297 enq.bits.status.firstIssue := false.B 298 enq.bits.status.issueTimer := "b11".U 299 enq.bits.status.deqPortIdx := 0.U 300 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 301 enq.bits.payload := s0_enqBits(enqIdx) 302 } 303 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 304 og0Resp := io.og0Resp(i) 305 } 306 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 307 og1Resp := io.og1Resp(i) 308 } 309 if (params.inVfSchd) { 310 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 311 og2Resp := io.og2Resp.get(i) 312 } 313 } 314 if (params.isLdAddrIQ || params.isHyAddrIQ) { 315 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 316 finalIssueResp := io.finalIssueResp.get(i) 317 } 318 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 319 memAddrIssueResp := io.memAddrIssueResp.get(i) 320 } 321 } 322 if (params.isVecLduIQ) { 323 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 324 resp := io.vecLoadIssueResp.get(i) 325 } 326 } 327 for(deqIdx <- 0 until params.numDeq) { 328 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 329 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 330 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 331 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 332 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 333 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 334 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 335 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 336 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 337 } 338 entriesIO.wakeUpFromWB := io.wakeupFromWB 339 entriesIO.wakeUpFromIQ := wakeupFromIQ 340 entriesIO.vlIsZero := io.vlIsZero 341 entriesIO.vlIsVlmax := io.vlIsVlmax 342 entriesIO.og0Cancel := io.og0Cancel 343 entriesIO.og1Cancel := io.og1Cancel 344 entriesIO.ldCancel := io.ldCancel 345 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 346 //output 347 fuTypeVec := entriesIO.fuType 348 deqEntryVec := entriesIO.deqEntry 349 cancelDeqVec := entriesIO.cancelDeqVec 350 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 351 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 352 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 353 } 354 355 356 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 357 358 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 359 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 360 ).reverse) 361 362 // if deq port can accept the uop 363 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 364 Cat(fuTypeVec.map(fuType => 365 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 366 ).reverse) 367 } 368 369 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 370 fuTypeVec.map(fuType => 371 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 372 } 373 374 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 375 val mergeFuBusy = { 376 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 377 else canIssueVec.asUInt 378 } 379 val mergeIntWbBusy = { 380 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 381 else mergeFuBusy 382 } 383 val mergefpWbBusy = { 384 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 385 else mergeIntWbBusy 386 } 387 val mergeVfWbBusy = { 388 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 389 else mergefpWbBusy 390 } 391 val mergeV0WbBusy = { 392 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 393 else mergeVfWbBusy 394 } 395 val mergeVlWbBusy = { 396 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 397 else mergeV0WbBusy 398 } 399 merge := mergeVlWbBusy 400 } 401 402 deqCanIssue.zipWithIndex.foreach { case (req, i) => 403 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 404 } 405 dontTouch(fuTypeVec) 406 dontTouch(canIssueMergeAllBusy) 407 dontTouch(deqCanIssue) 408 409 if (params.numDeq == 2) { 410 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 411 } 412 413 if (params.numDeq == 2 && params.deqFuSame) { 414 val subDeqPolicy = Module(new DeqPolicy()) 415 416 enqEntryOldestSel := DontCare 417 418 if (params.isAllComp || params.isAllSimp) { 419 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 420 enq = othersEntryEnqSelVec.get, 421 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 422 ) 423 othersEntryOldestSel(1) := DontCare 424 425 subDeqPolicy.io.request := subDeqRequest.get 426 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 427 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 428 } 429 else { 430 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 431 simpAgeDetectRequest.get(1) := DontCare 432 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 433 if (params.numEnq == 2) { 434 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 435 } 436 437 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 438 enq = simpEntryEnqSelVec.get, 439 canIssue = simpAgeDetectRequest.get 440 ) 441 442 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 443 enq = compEntryEnqSelVec.get, 444 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 445 ) 446 compEntryOldestSel.get(1) := DontCare 447 448 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 449 othersEntryOldestSel(0).bits := Cat( 450 compEntryOldestSel.get(0).bits, 451 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 452 ) 453 othersEntryOldestSel(1) := DontCare 454 455 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 456 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 457 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 458 } 459 460 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 461 462 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 463 deqSelValidVec(1) := subDeqSelValidVec.get(0) 464 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 465 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 466 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 467 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 468 469 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 470 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 471 selOH := deqOH 472 } 473 } 474 else { 475 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 476 enq = VecInit(s0_doEnqSelValidVec), 477 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 478 ) 479 480 if (params.isAllComp || params.isAllSimp) { 481 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 482 enq = othersEntryEnqSelVec.get, 483 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 484 ) 485 486 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 487 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 488 selValid := false.B 489 selOH := 0.U.asTypeOf(selOH) 490 } else { 491 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 492 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 493 } 494 } 495 } 496 else { 497 othersEntryOldestSel := DontCare 498 499 deqCanIssue.zipWithIndex.foreach { case (req, i) => 500 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 501 } 502 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 503 if (params.numEnq == 2) { 504 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 505 } 506 507 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 508 enq = simpEntryEnqSelVec.get, 509 canIssue = simpAgeDetectRequest.get 510 ) 511 512 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 513 enq = compEntryEnqSelVec.get, 514 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 515 ) 516 517 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 518 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 519 selValid := false.B 520 selOH := 0.U.asTypeOf(selOH) 521 } else { 522 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 523 selOH := Cat( 524 compEntryOldestSel.get(i).bits, 525 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 526 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 527 ) 528 } 529 } 530 } 531 532 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 533 selValid := deqValid && deqBeforeDly(i).ready 534 selOH := deqOH 535 } 536 } 537 538 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 539 540 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 541 deqResp.valid := finalDeqSelValidVec(i) 542 deqResp.bits.resp := RespType.success 543 deqResp.bits.robIdx := DontCare 544 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 545 deqResp.bits.uopIdx.foreach(_ := DontCare) 546 } 547 548 //fuBusyTable 549 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 550 if(busyTableWrite.nonEmpty) { 551 val btwr = busyTableWrite.get 552 val btrd = busyTableRead.get 553 btwr.io.in.deqResp := toBusyTableDeqResp(i) 554 btwr.io.in.og0Resp := io.og0Resp(i) 555 btwr.io.in.og1Resp := io.og1Resp(i) 556 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 557 btrd.io.in.fuTypeRegVec := fuTypeVec 558 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 559 } 560 else { 561 fuBusyTableMask(i) := 0.U(params.numEntries.W) 562 } 563 } 564 565 //wbfuBusyTable write 566 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 567 if(busyTableWrite.nonEmpty) { 568 val btwr = busyTableWrite.get 569 val bt = busyTable.get 570 val dq = deqResp.get 571 btwr.io.in.deqResp := toBusyTableDeqResp(i) 572 btwr.io.in.og0Resp := io.og0Resp(i) 573 btwr.io.in.og1Resp := io.og1Resp(i) 574 bt := btwr.io.out.fuBusyTable 575 dq := btwr.io.out.deqRespSet 576 } 577 } 578 579 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 580 if (busyTableWrite.nonEmpty) { 581 val btwr = busyTableWrite.get 582 val bt = busyTable.get 583 val dq = deqResp.get 584 btwr.io.in.deqResp := toBusyTableDeqResp(i) 585 btwr.io.in.og0Resp := io.og0Resp(i) 586 btwr.io.in.og1Resp := io.og1Resp(i) 587 bt := btwr.io.out.fuBusyTable 588 dq := btwr.io.out.deqRespSet 589 } 590 } 591 592 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 593 if (busyTableWrite.nonEmpty) { 594 val btwr = busyTableWrite.get 595 val bt = busyTable.get 596 val dq = deqResp.get 597 btwr.io.in.deqResp := toBusyTableDeqResp(i) 598 btwr.io.in.og0Resp := io.og0Resp(i) 599 btwr.io.in.og1Resp := io.og1Resp(i) 600 bt := btwr.io.out.fuBusyTable 601 dq := btwr.io.out.deqRespSet 602 } 603 } 604 605 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 606 if (busyTableWrite.nonEmpty) { 607 val btwr = busyTableWrite.get 608 val bt = busyTable.get 609 val dq = deqResp.get 610 btwr.io.in.deqResp := toBusyTableDeqResp(i) 611 btwr.io.in.og0Resp := io.og0Resp(i) 612 btwr.io.in.og1Resp := io.og1Resp(i) 613 bt := btwr.io.out.fuBusyTable 614 dq := btwr.io.out.deqRespSet 615 } 616 } 617 618 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 619 if (busyTableWrite.nonEmpty) { 620 val btwr = busyTableWrite.get 621 val bt = busyTable.get 622 val dq = deqResp.get 623 btwr.io.in.deqResp := toBusyTableDeqResp(i) 624 btwr.io.in.og0Resp := io.og0Resp(i) 625 btwr.io.in.og1Resp := io.og1Resp(i) 626 bt := btwr.io.out.fuBusyTable 627 dq := btwr.io.out.deqRespSet 628 } 629 } 630 631 //wbfuBusyTable read 632 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 633 if(busyTableRead.nonEmpty) { 634 val btrd = busyTableRead.get 635 val bt = busyTable.get 636 btrd.io.in.fuBusyTable := bt 637 btrd.io.in.fuTypeRegVec := fuTypeVec 638 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 639 } 640 else { 641 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 642 } 643 } 644 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 645 if (busyTableRead.nonEmpty) { 646 val btrd = busyTableRead.get 647 val bt = busyTable.get 648 btrd.io.in.fuBusyTable := bt 649 btrd.io.in.fuTypeRegVec := fuTypeVec 650 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 651 } 652 else { 653 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 654 } 655 } 656 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 657 if (busyTableRead.nonEmpty) { 658 val btrd = busyTableRead.get 659 val bt = busyTable.get 660 btrd.io.in.fuBusyTable := bt 661 btrd.io.in.fuTypeRegVec := fuTypeVec 662 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 663 } 664 else { 665 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 666 } 667 } 668 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 669 if (busyTableRead.nonEmpty) { 670 val btrd = busyTableRead.get 671 val bt = busyTable.get 672 btrd.io.in.fuBusyTable := bt 673 btrd.io.in.fuTypeRegVec := fuTypeVec 674 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 675 } 676 else { 677 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 678 } 679 } 680 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 681 if (busyTableRead.nonEmpty) { 682 val btrd = busyTableRead.get 683 val bt = busyTable.get 684 btrd.io.in.fuBusyTable := bt 685 btrd.io.in.fuTypeRegVec := fuTypeVec 686 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 687 } 688 else { 689 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 690 } 691 } 692 693 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 694 wakeUpQueueOption.foreach { 695 wakeUpQueue => 696 val flush = Wire(new WakeupQueueFlush) 697 flush.redirect := io.flush 698 flush.ldCancel := io.ldCancel 699 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 700 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 701 wakeUpQueue.io.flush := flush 702 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 703 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 704 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 705 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 706 } 707 } 708 709 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 710 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 711 deq.bits.addrOH := finalDeqSelOHVec(i) 712 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 713 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 714 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 715 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 716 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 717 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 718 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 719 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 720 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 721 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 722 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 723 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 724 725 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 726 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 727 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 728 deq.bits.common.srcTimer.foreach(_ := DontCare) 729 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 730 deq.bits.common.src := DontCare 731 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 732 733 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 734 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 735 rf.foreach(_.addr := psrc) 736 rf.foreach(_.srcType := srcType) 737 } 738 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 739 sink := source 740 } 741 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 742 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 743 744 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 745 deq.bits.common.perfDebugInfo.selectTime := GTimer() 746 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 747 } 748 749 io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 750 NewPipelineConnect( 751 deq, deqDly, deqDly.valid, 752 false.B, 753 Option("Scheduler2DataPathPipe") 754 ) 755 } 756 if(backendParams.debugEn) { 757 dontTouch(io.deqDelay) 758 } 759 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 760 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 761 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 762 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 763 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 764 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 765 } else if (wakeUpQueues(i).nonEmpty) { 766 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 767 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 768 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 769 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 770 } else { 771 wakeup.valid := false.B 772 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 773 wakeup.bits.is0Lat := 0.U 774 } 775 if (wakeUpQueues(i).nonEmpty) { 776 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 777 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 778 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 779 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 780 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 781 } 782 783 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 784 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 785 } 786 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 787 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 788 } 789 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 790 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 791 } 792 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 793 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 794 } 795 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 796 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 797 } 798 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 799 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 800 } 801 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 802 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 803 } 804 } 805 806 // Todo: better counter implementation 807 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 808 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 809 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 810 private val enqEntryValidCntDeq0 = PopCount( 811 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 812 ) 813 private val othersValidCntDeq0 = PopCount( 814 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 815 ) 816 private val enqEntryValidCntDeq1 = PopCount( 817 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 818 ) 819 private val othersValidCntDeq1 = PopCount( 820 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 821 ) 822 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 823 io.enq.map(_.bits.fuType).map(fuType => 824 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 825 } 826 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 827 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 828 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 829 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 830 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 831 for (i <- 0 until params.numEnq) { 832 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 833 } 834 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 835 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 836 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 837 } 838 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 839 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 840 841 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 842 io.status.empty := !Cat(validVec).orR 843 io.status.full := othersCanotIn 844 io.status.validCnt := PopCount(validVec) 845 846 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 847 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 848 } 849 850 // issue perf counter 851 // enq count 852 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 853 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 854 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 855 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 856 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 857 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 858 // valid count 859 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 860 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 861 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 862 // only split when more than 1 func type 863 if (params.getFuCfgs.size > 0) { 864 for (t <- FuType.functionNameMap.keys) { 865 val fuName = FuType.functionNameMap(t) 866 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 867 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 868 } 869 } 870 } 871 // ready instr count 872 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 873 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 874 // only split when more than 1 func type 875 if (params.getFuCfgs.size > 0) { 876 for (t <- FuType.functionNameMap.keys) { 877 val fuName = FuType.functionNameMap(t) 878 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 879 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 880 } 881 } 882 } 883 884 // deq instr count 885 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 886 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 887 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 888 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 889 890 // deq instr data source count 891 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 892 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 893 }.reduce(_ +& _)) 894 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 895 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 896 }.reduce(_ +& _)) 897 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 898 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 899 }.reduce(_ +& _)) 900 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 901 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 902 }.reduce(_ +& _)) 903 904 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 905 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 906 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 907 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 908 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 909 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 910 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 911 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 912 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 913 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 914 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 915 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 916 917 // deq instr data source count for each futype 918 for (t <- FuType.functionNameMap.keys) { 919 val fuName = FuType.functionNameMap(t) 920 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 921 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 922 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 923 }.reduce(_ +& _)) 924 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 925 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 926 }.reduce(_ +& _)) 927 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 928 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 929 }.reduce(_ +& _)) 930 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 931 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 932 }.reduce(_ +& _)) 933 934 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 935 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 936 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 937 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 938 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 939 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 940 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 941 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 942 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 943 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 944 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 945 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 946 } 947 } 948} 949 950class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 951 val fastMatch = UInt(backendParams.LduCnt.W) 952 val fastImm = UInt(12.W) 953} 954 955class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 956 957class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 958 extends IssueQueueImp(wrapper) 959{ 960 io.suggestName("none") 961 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 962 963 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 964 deq.bits.common.pc.foreach(_ := DontCare) 965 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 966 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 967 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 968 deq.bits.common.predictInfo.foreach(x => { 969 x.target := DontCare 970 x.taken := deqEntryVec(i).bits.payload.pred_taken 971 }) 972 // for std 973 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 974 // for i2f 975 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 976 }} 977} 978 979class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 980 extends IssueQueueImp(wrapper) 981{ 982 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 983 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 984 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 985 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 986 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 987 }} 988} 989 990class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 991 extends IssueQueueImp(wrapper) 992{ 993 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 994 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 995 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 996 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 997 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 998 }} 999} 1000 1001class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1002 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1003 1004 // TODO: is still needed? 1005 val checkWait = new Bundle { 1006 val stIssuePtr = Input(new SqPtr) 1007 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1008 } 1009 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1010 1011 // load wakeup 1012 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1013 1014 // vector 1015 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 1016 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 1017} 1018 1019class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1020 val memIO = Some(new IssueQueueMemBundle) 1021} 1022 1023class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1024 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1025 1026 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1027 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1028 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1029 1030 io.suggestName("none") 1031 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1032 private val memIO = io.memIO.get 1033 1034 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1035 1036 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1037 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1038 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1039 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1040 slowResp.bits.fuType := DontCare 1041 } 1042 1043 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1044 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1045 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1046 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1047 fastResp.bits.fuType := DontCare 1048 } 1049 1050 // load wakeup 1051 val loadWakeUpIter = memIO.loadWakeUp.iterator 1052 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1053 if (param.hasLoadExu) { 1054 require(wakeUpQueues(i).isEmpty) 1055 val uop = loadWakeUpIter.next() 1056 1057 wakeup.valid := GatedValidRegNext(uop.fire) 1058 wakeup.bits.rfWen := GatedValidRegNext(uop.bits.rfWen && uop.fire) 1059 wakeup.bits.fpWen := GatedValidRegNext(uop.bits.fpWen && uop.fire) 1060 wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire) 1061 wakeup.bits.v0Wen := GatedValidRegNext(uop.bits.v0Wen && uop.fire) 1062 wakeup.bits.vlWen := GatedValidRegNext(uop.bits.vlWen && uop.fire) 1063 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1064 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1065 1066 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen && uop.fire))) 1067 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen && uop.fire))) 1068 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire))) 1069 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.v0Wen && uop.fire))) 1070 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vlWen && uop.fire))) 1071 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1072 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1073 1074 wakeup.bits.is0Lat := 0.U 1075 } 1076 } 1077 require(!loadWakeUpIter.hasNext) 1078 1079 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1080 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1081 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1082 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1083 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1084 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1085 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1086 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1087 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1088 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1089 } 1090} 1091 1092class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1093 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1094 1095 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1096 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1097 1098 io.suggestName("none") 1099 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1100 private val memIO = io.memIO.get 1101 1102 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1103 1104 for (i <- entries.io.enq.indices) { 1105 entries.io.enq(i).bits.status match { case enqData => 1106 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1107 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1108 // MemAddrIQ also handle vector insts 1109 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1110 enqData.blocked := false.B 1111 } 1112 } 1113 1114 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1115 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1116 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1117 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1118 slowResp.bits.fuType := DontCare 1119 slowResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get 1120 } 1121 1122 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1123 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1124 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1125 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1126 fastResp.bits.fuType := DontCare 1127 fastResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get 1128 } 1129 1130 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1131 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1132 1133 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1134 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1135 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1136 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1137 if (params.isVecLduIQ) { 1138 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1139 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1140 } 1141 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1142 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1143 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1144 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1145 } 1146 1147 io.vecLoadIssueResp.foreach(dontTouch(_)) 1148} 1149