1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 54 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 55 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 56 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 57 val og0Cancel = Input(ExuOH(backendParams.numExu)) 58 val og1Cancel = Input(ExuOH(backendParams.numExu)) 59 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 60 61 // Outputs 62 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 63 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 64 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 65 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 66 67 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 68 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 69} 70 71class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 72 extends LazyModuleImp(wrapper) 73 with HasXSParameter { 74 75 override def desiredName: String = s"${params.getIQName}" 76 77 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 78 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 79 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 80 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 81 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 82 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 83 84 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 85 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 86 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 87 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 88 89 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 90 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 91 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 92 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 93 val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap) 94 95 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}") 96 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 97 lazy val io = IO(new IssueQueueIO()) 98 99 // Modules 100 val entries = Module(new Entries) 101 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 102 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 103 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 104 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 105 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 106 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 107 108 class WakeupQueueFlush extends Bundle { 109 val redirect = ValidIO(new Redirect) 110 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 111 val og0Fail = Output(Bool()) 112 val og1Fail = Output(Bool()) 113 } 114 115 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 116 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 117 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 118 val ogFailFlush = stage match { 119 case 1 => flush.og0Fail 120 case 2 => flush.og1Fail 121 case _ => false.B 122 } 123 redirectFlush || loadDependencyFlush || ogFailFlush 124 } 125 126 private def modificationFunc(exuInput: ExuInput): ExuInput = { 127 val newExuInput = WireDefault(exuInput) 128 newExuInput.loadDependency match { 129 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 130 case None => 131 } 132 newExuInput 133 } 134 135 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 136 val lastExuInput = WireDefault(exuInput) 137 val newExuInput = WireDefault(newInput) 138 newExuInput.elements.foreach { case (name, data) => 139 if (lastExuInput.elements.contains(name)) { 140 data := lastExuInput.elements(name) 141 } 142 } 143 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 144 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 145 } 146 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 147 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 148 } 149 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 150 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 151 } 152 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 153 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 154 } 155 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 156 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 157 } 158 newExuInput 159 } 160 161 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 162 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 163 ))} 164 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 165 166 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 167 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 168 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 169 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 170 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 171 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 172 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 173 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 175 val s0_enqValidVec = io.enq.map(_.valid) 176 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 177 val s0_enqNotFlush = !io.flush.valid 178 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 179 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 180 181 182 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 183 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 184 185 val validVec = VecInit(entries.io.valid.asBools) 186 val canIssueVec = VecInit(entries.io.canIssue.asBools) 187 dontTouch(canIssueVec) 188 val deqFirstIssueVec = entries.io.isFirstIssue 189 190 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 191 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 192 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 193 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 194 // (entryIdx)(srcIdx)(exuIdx) 195 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 196 val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer 197 198 // (deqIdx)(srcIdx)(exuIdx) 199 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 200 val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 201 202 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 203 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 204 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 207 //deq 208 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 209 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 210 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 211 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 212 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 213 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 214 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 215 216 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 217 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 218 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 219 220 //trans 221 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 222 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 223 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 224 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 225 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 226 227 /** 228 * Connection of [[entries]] 229 */ 230 entries.io match { case entriesIO: EntriesIO => 231 entriesIO.flush := io.flush 232 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 233 enq.valid := s0_doEnqSelValidVec(enqIdx) 234 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 235 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 236 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 237 for(j <- 0 until numLsrc) { 238 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 239 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 240 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 241 enq.bits.status.srcStatus(j).dataSources.value := DataSource.reg 242 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 243 if(params.hasIQWakeUp) { 244 enq.bits.status.srcStatus(j).srcTimer.get := 0.U(3.W) 245 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 246 } 247 } 248 enq.bits.status.blocked := false.B 249 enq.bits.status.issued := false.B 250 enq.bits.status.firstIssue := false.B 251 enq.bits.status.issueTimer := "b10".U 252 enq.bits.status.deqPortIdx := 0.U 253 if (params.isVecMemIQ) { 254 enq.bits.status.vecMem.get.uopIdx := s0_enqBits(enqIdx).uopIdx 255 } 256 if (params.inIntSchd && params.AluCnt > 0) { 257 // dirty code for lui+addi(w) fusion 258 val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32 259 val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0)) 260 enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm)) 261 } 262 else if (params.inMemSchd && params.LduCnt > 0) { 263 // dirty code for fused_lui_load 264 val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType) 265 enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm)) 266 } 267 else { 268 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 269 } 270 enq.bits.payload := s0_enqBits(enqIdx) 271 } 272 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 273 og0Resp := io.og0Resp(i) 274 } 275 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 276 og1Resp := io.og1Resp(i) 277 } 278 entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) => 279 finalIssueResp := io.finalIssueResp.get(i) 280 }) 281 for(deqIdx <- 0 until params.numDeq) { 282 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 283 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 284 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 285 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 286 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 287 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 288 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 289 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 290 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 291 } 292 entriesIO.wakeUpFromWB := io.wakeupFromWB 293 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 294 entriesIO.og0Cancel := io.og0Cancel 295 entriesIO.og1Cancel := io.og1Cancel 296 entriesIO.ldCancel := io.ldCancel 297 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 298 //output 299 fuTypeVec := entriesIO.fuType 300 deqEntryVec := entriesIO.deqEntry 301 cancelDeqVec := entriesIO.cancelDeqVec 302 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 303 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 304 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 305 } 306 307 308 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 309 310 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 311 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 312 ).reverse) 313 314 // if deq port can accept the uop 315 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 316 Cat(fuTypeVec.map(fuType => 317 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 318 ).reverse) 319 } 320 321 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 322 fuTypeVec.map(fuType => 323 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 324 } 325 326 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 327 val mergeFuBusy = { 328 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 329 else canIssueVec.asUInt 330 } 331 val mergeIntWbBusy = { 332 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 333 else mergeFuBusy 334 } 335 val mergeVfWbBusy = { 336 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 337 else mergeIntWbBusy 338 } 339 merge := mergeVfWbBusy 340 } 341 342 deqCanIssue.zipWithIndex.foreach { case (req, i) => 343 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 344 } 345 dontTouch(fuTypeVec) 346 dontTouch(canIssueMergeAllBusy) 347 dontTouch(deqCanIssue) 348 349 if (params.numDeq == 2) { 350 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 351 } 352 353 if (params.numDeq == 2 && params.deqFuSame) { 354 val subDeqPolicy = Module(new DeqPolicy()) 355 356 enqEntryOldestSel := DontCare 357 358 if (params.isAllComp || params.isAllSimp) { 359 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 360 enq = othersEntryEnqSelVec.get, 361 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 362 ) 363 othersEntryOldestSel(1) := DontCare 364 365 subDeqPolicy.io.request := subDeqRequest.get 366 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 367 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 368 } 369 else { 370 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 371 simpAgeDetectRequest.get(1) := DontCare 372 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 373 if (params.numEnq == 2) { 374 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 375 } 376 377 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 378 enq = simpEntryEnqSelVec.get, 379 canIssue = simpAgeDetectRequest.get 380 ) 381 382 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 383 enq = compEntryEnqSelVec.get, 384 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 385 ) 386 compEntryOldestSel.get(1) := DontCare 387 388 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 389 othersEntryOldestSel(0).bits := Cat( 390 compEntryOldestSel.get(0).bits, 391 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 392 ) 393 othersEntryOldestSel(1) := DontCare 394 395 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 396 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 397 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 398 } 399 400 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 401 402 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 403 deqSelValidVec(1) := subDeqSelValidVec.get(0) 404 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 405 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 406 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 407 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 408 409 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 410 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 411 selOH := deqOH 412 } 413 } 414 else { 415 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 416 enq = VecInit(s0_doEnqSelValidVec), 417 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 418 ) 419 420 if (params.isAllComp || params.isAllSimp) { 421 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 422 enq = othersEntryEnqSelVec.get, 423 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 424 ) 425 426 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 427 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 428 selValid := false.B 429 selOH := 0.U.asTypeOf(selOH) 430 } else { 431 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 432 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 433 } 434 } 435 } 436 else { 437 othersEntryOldestSel := DontCare 438 439 deqCanIssue.zipWithIndex.foreach { case (req, i) => 440 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 441 } 442 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 443 if (params.numEnq == 2) { 444 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 445 } 446 447 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 448 enq = simpEntryEnqSelVec.get, 449 canIssue = simpAgeDetectRequest.get 450 ) 451 452 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 453 enq = compEntryEnqSelVec.get, 454 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 455 ) 456 457 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 458 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 459 selOH := Cat( 460 compEntryOldestSel.get(i).bits, 461 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 462 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 463 ) 464 } 465 } 466 467 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 468 selValid := deqValid && deqBeforeDly(i).ready 469 selOH := deqOH 470 } 471 } 472 473 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 474 475 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 476 deqResp.valid := finalDeqSelValidVec(i) 477 deqResp.bits.resp := RespType.success 478 deqResp.bits.robIdx := DontCare 479 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 480 deqResp.bits.uopIdx.foreach(_ := DontCare) 481 } 482 483 //fuBusyTable 484 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 485 if(busyTableWrite.nonEmpty) { 486 val btwr = busyTableWrite.get 487 val btrd = busyTableRead.get 488 btwr.io.in.deqResp := toBusyTableDeqResp(i) 489 btwr.io.in.og0Resp := io.og0Resp(i) 490 btwr.io.in.og1Resp := io.og1Resp(i) 491 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 492 btrd.io.in.fuTypeRegVec := fuTypeVec 493 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 494 } 495 else { 496 fuBusyTableMask(i) := 0.U(params.numEntries.W) 497 } 498 } 499 500 //wbfuBusyTable write 501 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 502 if(busyTableWrite.nonEmpty) { 503 val btwr = busyTableWrite.get 504 val bt = busyTable.get 505 val dq = deqResp.get 506 btwr.io.in.deqResp := toBusyTableDeqResp(i) 507 btwr.io.in.og0Resp := io.og0Resp(i) 508 btwr.io.in.og1Resp := io.og1Resp(i) 509 bt := btwr.io.out.fuBusyTable 510 dq := btwr.io.out.deqRespSet 511 } 512 } 513 514 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 515 if (busyTableWrite.nonEmpty) { 516 val btwr = busyTableWrite.get 517 val bt = busyTable.get 518 val dq = deqResp.get 519 btwr.io.in.deqResp := toBusyTableDeqResp(i) 520 btwr.io.in.og0Resp := io.og0Resp(i) 521 btwr.io.in.og1Resp := io.og1Resp(i) 522 bt := btwr.io.out.fuBusyTable 523 dq := btwr.io.out.deqRespSet 524 } 525 } 526 527 //wbfuBusyTable read 528 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 529 if(busyTableRead.nonEmpty) { 530 val btrd = busyTableRead.get 531 val bt = busyTable.get 532 btrd.io.in.fuBusyTable := bt 533 btrd.io.in.fuTypeRegVec := fuTypeVec 534 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 535 } 536 else { 537 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 538 } 539 } 540 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 541 if (busyTableRead.nonEmpty) { 542 val btrd = busyTableRead.get 543 val bt = busyTable.get 544 btrd.io.in.fuBusyTable := bt 545 btrd.io.in.fuTypeRegVec := fuTypeVec 546 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 547 } 548 else { 549 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 550 } 551 } 552 553 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 554 wakeUpQueueOption.foreach { 555 wakeUpQueue => 556 val flush = Wire(new WakeupQueueFlush) 557 flush.redirect := io.flush 558 flush.ldCancel := io.ldCancel 559 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 560 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 561 wakeUpQueue.io.flush := flush 562 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 563 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 564 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 565 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 566 } 567 } 568 569 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 570 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 571 deq.bits.addrOH := finalDeqSelOHVec(i) 572 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 573 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 574 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 575 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 576 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 577 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 578 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 579 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 580 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 581 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 582 583 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 584 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 585 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 586 deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i)) 587 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 588 deq.bits.common.src := DontCare 589 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 590 591 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 592 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 593 rf.foreach(_.addr := psrc) 594 rf.foreach(_.srcType := srcType) 595 } 596 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 597 sink := source 598 } 599 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 600 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 601 602 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 603 deq.bits.common.perfDebugInfo.selectTime := GTimer() 604 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 605 } 606 607 private val deqShift = WireDefault(deqBeforeDly) 608 deqShift.zip(deqBeforeDly).foreach { 609 case (shifted, original) => 610 original.ready := shifted.ready // this will not cause combinational loop 611 shifted.bits.common.loadDependency.foreach( 612 _ := original.bits.common.loadDependency.get.map(_ << 1) 613 ) 614 } 615 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 616 NewPipelineConnect( 617 deq, deqDly, deqDly.valid, 618 false.B, 619 Option("Scheduler2DataPathPipe") 620 ) 621 } 622 if(backendParams.debugEn) { 623 dontTouch(io.deqDelay) 624 } 625 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 626 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 627 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 628 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 629 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 630 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 631 } else if (wakeUpQueues(i).nonEmpty) { 632 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 633 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 634 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 635 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 636 } else { 637 wakeup.valid := false.B 638 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 639 wakeup.bits.is0Lat := 0.U 640 } 641 if (wakeUpQueues(i).nonEmpty) { 642 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 643 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 644 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 645 } 646 647 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 648 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 649 } 650 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 651 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 652 } 653 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 654 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 655 } 656 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 657 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 658 } 659 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 660 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 661 } 662 } 663 664 // Todo: better counter implementation 665 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 666 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 667 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 668 private val enqEntryValidCntDeq0 = PopCount( 669 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 670 ) 671 private val othersValidCntDeq0 = PopCount( 672 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 673 ) 674 private val enqEntryValidCntDeq1 = PopCount( 675 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 676 ) 677 private val othersValidCntDeq1 = PopCount( 678 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 679 ) 680 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 681 io.enq.map(_.bits.fuType).map(fuType => 682 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 683 } 684 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 685 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 686 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 +& enqValidCntDeq0 - deqBeforeDly.head.fire) // validCntDeqVec(0) 687 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 +& enqValidCntDeq1 - deqBeforeDly.last.fire) // validCntDeqVec(1) 688 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 689 for (i <- 0 until params.numEnq) { 690 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 691 } 692 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 693 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 694 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 695 } 696 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 697 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 698 699 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 700 io.status.empty := !Cat(validVec).orR 701 io.status.full := othersCanotIn 702 io.status.validCnt := PopCount(validVec) 703 704 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 705 Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 706 } 707 708 // issue perf counter 709 // enq count 710 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 711 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 712 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 713 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 714 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 715 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 716 // valid count 717 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 718 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 719 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 720 // only split when more than 1 func type 721 if (params.getFuCfgs.size > 0) { 722 for (t <- FuType.functionNameMap.keys) { 723 val fuName = FuType.functionNameMap(t) 724 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 725 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 726 } 727 } 728 } 729 // ready instr count 730 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 731 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 732 // only split when more than 1 func type 733 if (params.getFuCfgs.size > 0) { 734 for (t <- FuType.functionNameMap.keys) { 735 val fuName = FuType.functionNameMap(t) 736 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 737 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 738 } 739 } 740 } 741 742 // deq instr count 743 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 744 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 745 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 746 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 747 748 // deq instr data source count 749 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 750 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 751 }.reduce(_ +& _)) 752 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 753 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 754 }.reduce(_ +& _)) 755 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 756 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 757 }.reduce(_ +& _)) 758 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 759 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 760 }.reduce(_ +& _)) 761 762 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 763 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 764 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 765 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 766 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 767 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 768 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 769 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 770 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 771 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 772 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 773 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 774 775 // deq instr data source count for each futype 776 for (t <- FuType.functionNameMap.keys) { 777 val fuName = FuType.functionNameMap(t) 778 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 779 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 780 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 781 }.reduce(_ +& _)) 782 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 783 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 784 }.reduce(_ +& _)) 785 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 786 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 787 }.reduce(_ +& _)) 788 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 789 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 790 }.reduce(_ +& _)) 791 792 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 793 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 794 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 795 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 796 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 797 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 798 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 799 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 800 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 801 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 802 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 803 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 804 } 805 } 806 807 // cancel instr count 808 if (params.hasIQWakeUp) { 809 val cancelVec: Vec[Bool] = entries.io.cancel.get 810 XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2))) 811 XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1) 812 for (t <- FuType.functionNameMap.keys) { 813 val fuName = FuType.functionNameMap(t) 814 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 815 XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U })) 816 XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1) 817 } 818 } 819 } 820} 821 822class IssueQueueJumpBundle extends Bundle { 823 val pc = UInt(VAddrData().dataWidth.W) 824} 825 826class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 827 val fastMatch = UInt(backendParams.LduCnt.W) 828 val fastImm = UInt(12.W) 829} 830 831class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 832 833class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 834 extends IssueQueueImp(wrapper) 835{ 836 io.suggestName("none") 837 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 838 839 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 840 deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc) 841 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 842 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 843 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 844 deq.bits.common.predictInfo.foreach(x => { 845 x.target := DontCare 846 x.taken := deqEntryVec(i).bits.payload.pred_taken 847 }) 848 // for std 849 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 850 // for i2f 851 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 852 }} 853} 854 855class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 856 extends IssueQueueImp(wrapper) 857{ 858 s0_enqBits.foreach{ x => 859 x.srcType(3) := SrcType.vp // v0: mask src 860 x.srcType(4) := SrcType.vp // vl&vtype 861 } 862 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 863 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 864 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 865 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 866 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 867 }} 868} 869 870class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 871 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 872 val checkWait = new Bundle { 873 val stIssuePtr = Input(new SqPtr) 874 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 875 } 876 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 877 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 878 879 // vector 880 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 881 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 882} 883 884class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 885 val memIO = Some(new IssueQueueMemBundle) 886} 887 888class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 889 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 890 891 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 892 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 893 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 894 895 io.suggestName("none") 896 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 897 private val memIO = io.memIO.get 898 899 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 900 901 for (i <- io.enq.indices) { 902 val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr) 903 val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => { 904 memIO.checkWait.memWaitUpdateReq.robIdx(i).valid && 905 memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value 906 })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready 907 s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased 908 // when have vpu 909 if (params.VlduCnt > 0 || params.VstuCnt > 0) { 910 s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src 911 s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype 912 } 913 } 914 915 for (i <- entries.io.enq.indices) { 916 entries.io.enq(i).bits.status match { case enqData => 917 enqData.blocked := false.B // s0_enqBits(i).loadWaitBit 918 enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict 919 enqData.mem.get.waitForStd := false.B 920 enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx 921 enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later 922 enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx 923 } 924 } 925 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 926 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 927 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 928 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 929 slowResp.bits.fuType := DontCare 930 } 931 932 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 933 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 934 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 935 fastResp.bits.resp := RespType.block 936 fastResp.bits.fuType := DontCare 937 } 938 939 entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq 940 entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr 941 942 // load wakeup 943 val loadWakeUpIter = memIO.loadWakeUp.iterator 944 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 945 if (param.hasLoadExu) { 946 require(wakeUpQueues(i).isEmpty) 947 val uop = loadWakeUpIter.next() 948 949 wakeup.valid := RegNext(uop.fire) 950 wakeup.bits.rfWen := RegNext(uop.bits.rfWen && uop.fire) 951 wakeup.bits.fpWen := RegNext(uop.bits.fpWen && uop.fire) 952 wakeup.bits.vecWen := RegNext(uop.bits.vecWen && uop.fire) 953 wakeup.bits.pdest := RegNext(uop.bits.pdest) 954 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 955 956 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.rfWen && uop.fire))) 957 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.fpWen && uop.fire))) 958 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := RegNext(uop.bits.vecWen && uop.fire))) 959 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegNext(uop.bits.pdest))) 960 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 961 962 wakeup.bits.is0Lat := 0.U 963 } 964 } 965 require(!loadWakeUpIter.hasNext) 966 967 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 968 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 969 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 970 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 971 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 972 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 973 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 974 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 975 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 976 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 977 // when have vpu 978 if (params.VlduCnt > 0 || params.VstuCnt > 0) { 979 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 980 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 981 } 982 } 983} 984 985class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 986 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 987 988 require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 989 990 io.suggestName("none") 991 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 992 private val memIO = io.memIO.get 993 994 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 995 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 996 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 997 (if (j < i) !valid(j) || compareVec(i)(j) 998 else if (j == i) valid(i) 999 else !valid(j) || !compareVec(j)(i)) 1000 )).andR)) 1001 resultOnehot 1002 } 1003 1004 val robIdxVec = entries.io.robIdx.get 1005 val uopIdxVec = entries.io.uopIdx.get 1006 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 1007 1008 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 1009 finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 1010 1011 if (params.isVecMemAddrIQ) { 1012 s0_enqBits.foreach{ x => 1013 x.srcType(3) := SrcType.vp // v0: mask src 1014 x.srcType(4) := SrcType.vp // vl&vtype 1015 } 1016 1017 for (i <- io.enq.indices) { 1018 s0_enqBits(i).loadWaitBit := false.B 1019 } 1020 1021 for (i <- entries.io.enq.indices) { 1022 entries.io.enq(i).bits.status match { case enqData => 1023 enqData.blocked := false.B // s0_enqBits(i).loadWaitBit 1024 enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict 1025 enqData.mem.get.waitForStd := false.B 1026 enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx 1027 enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later 1028 enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx 1029 } 1030 1031 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1032 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1033 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1034 slowResp.bits.resp := RespType.block 1035 slowResp.bits.fuType := DontCare 1036 } 1037 1038 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1039 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1040 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1041 fastResp.bits.resp := RespType.block 1042 fastResp.bits.fuType := DontCare 1043 } 1044 1045 entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq 1046 entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr 1047 } 1048 } 1049 1050 for (i <- entries.io.enq.indices) { 1051 entries.io.enq(i).bits.status.vecMem.get match { 1052 case enqData => 1053 enqData.sqIdx := s0_enqBits(i).sqIdx 1054 enqData.lqIdx := s0_enqBits(i).lqIdx 1055 enqData.uopIdx := s0_enqBits(i).uopIdx 1056 } 1057 } 1058 1059 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1060 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1061 1062 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (resp, i) => 1063 resp.bits.uopIdx.get := 0.U // Todo 1064 } 1065 1066 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (resp, i) => 1067 resp.bits.uopIdx.get := 0.U // Todo 1068 } 1069 1070 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1071 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1072 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx) 1073 if (params.isVecLdAddrIQ) { 1074 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1075 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1076 } 1077 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1078 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1079 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1080 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1081 } 1082} 1083