xref: /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala (revision 99ce5576f0ecce1b5045b7bc0dbbb2debd934fbb) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.{HasCircularQueuePtrHelper, GatedValidRegNext}
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{SqPtr, LqPtr}
15import xiangshan.mem.Bundles.MemWaitUpdateReqBundle
16
17
18class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
19  //input
20  val commonIn        = new CommonInBundle
21  //output
22  val commonOut       = new CommonOutBundle
23
24  def wakeup          = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
25}
26
27class OthersEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
28  val io = IO(new OthersEntryIO)
29
30  val common          = Wire(new CommonWireBundle)
31  val entryUpdate     = Wire(new EntryBundle)
32  val entryRegNext    = Wire(new EntryBundle)
33  val hasWakeupIQ     = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
34
35  //Reg
36  val validReg = GatedValidRegNext(common.validRegNext, false.B)
37  val entryReg = RegNext(entryRegNext)
38
39  //Wire
40  CommonWireConnect(common, hasWakeupIQ, validReg, entryReg.status, io.commonIn, false)
41
42  if (params.hasIQWakeUp) {
43    ShiftLoadDependency(hasWakeupIQ.get)
44    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, entryReg.status, io.commonIn, false)
45  }
46
47  when(io.commonIn.enq.valid) {
48    assert(common.enqReady, s"${params.getIQName}'s OthersEntry is not ready when enq is valid\n")
49  }
50
51  when(io.commonIn.enq.valid) {
52    entryRegNext := io.commonIn.enq.bits
53  }.otherwise {
54    entryRegNext := entryUpdate
55  }
56
57  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false, isComp)
58
59  //output
60  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false, isComp)
61}
62
63class OthersEntryVecMem(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry(isComp)
64  with HasCircularQueuePtrHelper {
65
66  require(params.isVecMemIQ, "OthersEntryVecMem can only be instance of VecMem IQ")
67
68  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate)
69}
70
71object OthersEntry {
72  def apply(isComp: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams): OthersEntry = {
73    iqParams.schdType match {
74      case IntScheduler() => new OthersEntry(isComp)
75      case FpScheduler()  => new OthersEntry(isComp)
76      case MemScheduler() =>
77        if (iqParams.isVecMemIQ) new OthersEntryVecMem(isComp)
78        else new OthersEntry(isComp)
79      case VfScheduler() => new OthersEntry(isComp)
80      case _ => null
81    }
82  }
83}
84