1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 53 val fromCtrlBlock = new Bundle { 54 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuOH(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuOH(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 88 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 89 90 val finalBlockMem = OptionWrapper(params.isMemSchd, MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.numExu, Input(Bool())))))) 91 92 val memIO = if (params.isMemSchd) Some(new Bundle { 93 val lsqEnqIO = Flipped(new LsqEnqIO) 94 }) else None 95 val fromMem = if (params.isMemSchd) Some(new Bundle { 96 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 97 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 98 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 99 val stIssuePtr = Input(new SqPtr()) 100 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 101 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 102 val lqDeqPtr = Input(new LqPtr) 103 val sqDeqPtr = Input(new SqPtr) 104 // from lsq 105 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 106 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 107 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 108 }) else None 109 val toMem = if (params.isMemSchd) Some(new Bundle { 110 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 111 }) else None 112} 113 114abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 115 extends LazyModuleImp(wrapper) 116 with HasXSParameter 117{ 118 val io = IO(new SchedulerIO()) 119 120 // alias 121 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 122 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 123 private val schdType = params.schdType 124 125 // Modules 126 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 127 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 128 129 // valid count 130 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 131 132 // BusyTable Modules 133 val intBusyTable = schdType match { 134 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 135 case _ => None 136 } 137 138 val vfBusyTable = schdType match { 139 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 140 case _ => None 141 } 142 143 dispatch2Iq.io match { case dp2iq => 144 dp2iq.redirect <> io.fromCtrlBlock.flush 145 dp2iq.in <> io.fromDispatch.uops 146 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 147 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 148 } 149 150 intBusyTable match { 151 case Some(bt) => 152 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 153 btAllocPregs.valid := dpAllocPregs.isInt 154 btAllocPregs.bits := dpAllocPregs.preg 155 } 156 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 157 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 158 wb.bits := io.intWriteBack(i).addr 159 } 160 bt.io.wakeUp := io.fromSchedulers.wakeupVec 161 bt.io.cancel := io.fromDataPath.cancelToBusyTable 162 bt.io.ldCancel := io.ldCancel 163 case None => 164 } 165 166 vfBusyTable match { 167 case Some(bt) => 168 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 169 btAllocPregs.valid := dpAllocPregs.isFp 170 btAllocPregs.bits := dpAllocPregs.preg 171 } 172 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 173 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 174 wb.bits := io.vfWriteBack(i).addr 175 } 176 bt.io.wakeUp := io.fromSchedulers.wakeupVec 177 bt.io.cancel := io.fromDataPath.cancelToBusyTable 178 bt.io.ldCancel := io.ldCancel 179 case None => 180 } 181 182 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 183 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 184 185 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 186 sink.valid := source.wen 187 sink.bits.rfWen := source.intWen 188 sink.bits.fpWen := source.fpWen 189 sink.bits.vecWen := source.vecWen 190 sink.bits.pdest := source.addr 191 } 192 193 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 194 sink.valid := source.wen 195 sink.bits.rfWen := source.intWen 196 sink.bits.fpWen := source.fpWen 197 sink.bits.vecWen := source.vecWen 198 sink.bits.pdest := source.addr 199 } 200 201 // Connect bundles having the same wakeup source 202 issueQueues.zipWithIndex.foreach { case(iq, i) => 203 iq.io.wakeupFromIQ.foreach { wakeUp => 204 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 205 val exuIdx = wakeUp.bits.exuIdx 206 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 207 connectSamePort(wakeUp,wakeUpIn) 208 backendParams.connectWakeup(exuIdx) 209 if (backendParams.isCopyPdest(exuIdx)) { 210 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 211 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 212 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 213 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 214 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 215 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 216 } 217 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 218 if (iq.params.numFpSrc == 0) wakeUp.bits.fpWen := false.B 219 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 220 } 221 iq.io.og0Cancel := io.fromDataPath.og0Cancel 222 iq.io.og1Cancel := io.fromDataPath.og1Cancel 223 iq.io.ldCancel := io.ldCancel 224 if(params.isMemSchd) { 225 iq.io.finalBlock.zip(io.finalBlockMem.get(i)).foreach(x => x._1 := x._2) 226 } else { 227 iq.io.finalBlock.foreach(_ := false.B) 228 } 229 } 230 231 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 232 issueQueues.flatMap(_.io.wakeupToIQ) 233 .map(x => (x.bits.exuIdx, x)) 234 .toMap 235 236 // Connect bundles having the same wakeup source 237 io.toSchedulers.wakeupVec.foreach { wakeUp => 238 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 239 } 240 241 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 242 toDpDy <> issueQueues(i).io.deqDelay 243 } 244 245 // Response 246 issueQueues.zipWithIndex.foreach { case (iq, i) => 247 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 248 og0Resp := io.fromDataPath(i)(j).og0resp 249 } 250 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 251 og1Resp := io.fromDataPath(i)(j).og1resp 252 } 253 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 254 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 255 finalIssueResp := io.loadFinalIssueResp(i)(j) 256 } else { 257 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 258 } 259 }) 260 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 261 memAddrIssueResp := io.memAddrIssueResp(i)(j) 262 }) 263 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 264 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 265 } 266 267 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 268 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 269 270 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 271 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 272} 273 274class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 275 extends SchedulerImpBase(wrapper) 276 with HasXSParameter 277{ 278// dontTouch(io.vfWbFuBusyTable) 279 println(s"[SchedulerArithImp] " + 280 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 281 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 282 283 issueQueues.zipWithIndex.foreach { case (iq, i) => 284 iq.io.flush <> io.fromCtrlBlock.flush 285 iq.io.enq <> dispatch2Iq.io.out(i) 286 val intWBIQ = params.schdType match { 287 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 288 case VfScheduler() => wakeupFromVfWBVec 289 } 290 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 291 } 292} 293 294// FIXME: Vector mem instructions may not be handled properly! 295class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 296 extends SchedulerImpBase(wrapper) 297 with HasXSParameter 298{ 299 println(s"[SchedulerMemImp] " + 300 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 301 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 302 303 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 304 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0 || iq.params.VstaCnt > 0) // included in memAddrIQs 305 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0 || iq.params.VlduCnt > 0) 306 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0 || iq.params.VstdCnt > 0) 307 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 308 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 309 310 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 311 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 312 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 313 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 314 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 315 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 316 317 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 318 319 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 320 iq.io.flush <> io.fromCtrlBlock.flush 321 iq.io.enq <> dispatch2Iq.io.out(i) 322 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 323 } 324 325 ldAddrIQs.zipWithIndex.foreach { 326 case (imp: IssueQueueMemAddrImp, i) => 327 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 328 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 329 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 330 case _ => 331 } 332 333 stAddrIQs.zipWithIndex.foreach { 334 case (imp: IssueQueueMemAddrImp, i) => 335 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 336 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 337 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 338 case _ => 339 } 340 341 hyuIQs.zip(hyuIQIdxs).foreach { 342 case (imp: IssueQueueMemAddrImp, idx) => 343 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 344 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 345 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 346 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 347 // TODO: refactor ditry code 348 imp.io.deqDelay(1).ready := false.B 349 io.toDataPathAfterDelay(idx)(1).valid := false.B 350 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 351 case _ => 352 } 353 354 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 355 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 356 357 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 358 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 359 360 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 361 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 362 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 363 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 364 365 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 366 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 367 368 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 369 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 370 371 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 372 dispatch2Iq.io.out(idxInSchBlk).zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 373 val isAllReady = staIQ.ready && stdIQ.ready 374 dp.ready := isAllReady 375 staIQ.valid := dp.valid && isAllReady 376 stdIQ.valid := dp.valid && isAllReady && FuType.isStore(dp.bits.fuType) 377 } 378 } 379 380 for ((idxInSchBlk, i) <- hyaIdxSeq.zipWithIndex) { 381 dispatch2Iq.io.out(idxInSchBlk).zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 382 val isAllReady = hyaIQ.ready && hydIQ.ready 383 dp.ready := isAllReady 384 hyaIQ.valid := dp.valid && isAllReady 385 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 386 } 387 } 388 389 stDataIQs.zipWithIndex.foreach { case (iq, i) => 390 iq.io.flush <> io.fromCtrlBlock.flush 391 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 392 } 393 394 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 395 stdIQEnq.bits := staIQEnq.bits 396 // Store data reuses store addr src(1) in dispatch2iq 397 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 398 // \ 399 // ---src*(1)--> [stdIQ] 400 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 401 // instead of dispatch2Iq.io.out(x).bits.src*(1) 402 val stdIdx = 1 403 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 404 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 405 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 406 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 407 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 408 } 409 410 vecMemIQs.foreach { 411 case imp: IssueQueueVecMemImp => 412 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 413 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 414 // not used 415 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 416 // maybe not used 417 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 418 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 419 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 420 421 case _ => 422 } 423 424 val lsqEnqCtrl = Module(new LsqEnqCtrl) 425 426 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 427 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 428 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 429 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 430 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 431 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 432 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 433} 434