1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 val IQValidNumVec = Output(MixedVec(backendParams.genIQValidNumBundle)) 53 54 val fromCtrlBlock = new Bundle { 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val vlWriteBack = new Bundle { 68 val vlIsZero = Input(Bool()) 69 val vlIsVlmax = Input(Bool()) 70 } 71 72 val fromSchedulers = new Bundle { 73 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 74 } 75 76 val toSchedulers = new Bundle { 77 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 78 } 79 80 val fromDataPath = new Bundle { 81 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 82 val og0Cancel = Input(ExuOH(backendParams.numExu)) 83 // Todo: remove this after no cancel signal from og1 84 val og1Cancel = Input(ExuOH(backendParams.numExu)) 85 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 86 // just be compatible to old code 87 def apply(i: Int)(j: Int) = resp(i)(j) 88 } 89 90 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 91 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 92 val vecLoadIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.VlduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 93 94 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 95 96 val memIO = if (params.isMemSchd) Some(new Bundle { 97 val lsqEnqIO = Flipped(new LsqEnqIO) 98 }) else None 99 val fromMem = if (params.isMemSchd) Some(new Bundle { 100 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 101 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 102 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 103 val vstuFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 104 val vlduFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 105 val stIssuePtr = Input(new SqPtr()) 106 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 107 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 108 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 109 val lqDeqPtr = Input(new LqPtr) 110 val sqDeqPtr = Input(new SqPtr) 111 // from lsq 112 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 113 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 114 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 115 }) else None 116 val toMem = if (params.isMemSchd) Some(new Bundle { 117 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 118 }) else None 119} 120 121abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 122 extends LazyModuleImp(wrapper) 123 with HasXSParameter 124{ 125 val io = IO(new SchedulerIO()) 126 127 // alias 128 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 129 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 130 private val schdType = params.schdType 131 132 // Modules 133 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 134 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 135 if (params.isIntSchd) { 136 dispatch2Iq.io.IQValidNumVec.get := io.IQValidNumVec 137 io.IQValidNumVec := MixedVecInit(issueQueues.map(_.io.validCntDeqVec)) 138 } 139 else io.IQValidNumVec := 0.U.asTypeOf(io.IQValidNumVec) 140 141 // valid count 142 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 143 144 // BusyTable Modules 145 val intBusyTable = schdType match { 146 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 147 case _ => None 148 } 149 150 val vfBusyTable = schdType match { 151 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 152 case _ => None 153 } 154 155 dispatch2Iq.io match { case dp2iq => 156 dp2iq.redirect <> io.fromCtrlBlock.flush 157 dp2iq.in <> io.fromDispatch.uops 158 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 159 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 160 } 161 162 intBusyTable match { 163 case Some(bt) => 164 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 165 btAllocPregs.valid := dpAllocPregs.isInt 166 btAllocPregs.bits := dpAllocPregs.preg 167 } 168 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 169 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 170 wb.bits := io.intWriteBack(i).addr 171 } 172 bt.io.wakeUp := io.fromSchedulers.wakeupVec 173 bt.io.cancel := io.fromDataPath.cancelToBusyTable 174 bt.io.ldCancel := io.ldCancel 175 case None => 176 } 177 178 vfBusyTable match { 179 case Some(bt) => 180 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 181 btAllocPregs.valid := dpAllocPregs.isFp 182 btAllocPregs.bits := dpAllocPregs.preg 183 } 184 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 185 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 186 wb.bits := io.vfWriteBack(i).addr 187 } 188 bt.io.wakeUp := io.fromSchedulers.wakeupVec 189 bt.io.cancel := io.fromDataPath.cancelToBusyTable 190 bt.io.ldCancel := io.ldCancel 191 case None => 192 } 193 194 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 195 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 196 197 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 198 sink.valid := source.wen 199 sink.bits.rfWen := source.intWen 200 sink.bits.fpWen := source.fpWen 201 sink.bits.vecWen := source.vecWen 202 sink.bits.pdest := source.addr 203 } 204 205 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 206 sink.valid := source.wen 207 sink.bits.rfWen := source.intWen 208 sink.bits.fpWen := source.fpWen 209 sink.bits.vecWen := source.vecWen 210 sink.bits.pdest := source.addr 211 } 212 213 // Connect bundles having the same wakeup source 214 issueQueues.zipWithIndex.foreach { case(iq, i) => 215 iq.io.wakeupFromIQ.foreach { wakeUp => 216 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 217 val exuIdx = wakeUp.bits.exuIdx 218 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 219 connectSamePort(wakeUp,wakeUpIn) 220 backendParams.connectWakeup(exuIdx) 221 if (backendParams.isCopyPdest(exuIdx)) { 222 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 223 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 224 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 225 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 226 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 227 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 228 } 229 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 230 if (iq.params.numVfSrc == 0) wakeUp.bits.fpWen := false.B 231 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 232 } 233 iq.io.og0Cancel := io.fromDataPath.og0Cancel 234 iq.io.og1Cancel := io.fromDataPath.og1Cancel 235 iq.io.ldCancel := io.ldCancel 236 } 237 238 // connect the vl writeback informatino to the issue queues 239 issueQueues.zipWithIndex.foreach { case(iq, i) => 240 iq.io.vlIsVlmax := io.vlWriteBack.vlIsVlmax 241 iq.io.vlIsZero := io.vlWriteBack.vlIsZero 242 } 243 244 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 245 issueQueues.flatMap(_.io.wakeupToIQ) 246 .map(x => (x.bits.exuIdx, x)) 247 .toMap 248 249 // Connect bundles having the same wakeup source 250 io.toSchedulers.wakeupVec.foreach { wakeUp => 251 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 252 } 253 254 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 255 toDpDy <> issueQueues(i).io.deqDelay 256 } 257 258 // Response 259 issueQueues.zipWithIndex.foreach { case (iq, i) => 260 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 261 og0Resp := io.fromDataPath(i)(j).og0resp 262 } 263 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 264 og1Resp := io.fromDataPath(i)(j).og1resp 265 } 266 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 267 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 268 finalIssueResp := io.loadFinalIssueResp(i)(j) 269 } else { 270 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 271 } 272 }) 273 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 274 if (io.memAddrIssueResp(i).isDefinedAt(j)) { 275 memAddrIssueResp := io.memAddrIssueResp(i)(j) 276 } else { 277 memAddrIssueResp := 0.U.asTypeOf(memAddrIssueResp) 278 } 279 }) 280 iq.io.vecLoadIssueResp.foreach(_.zipWithIndex.foreach { case (resp, deqIdx) => 281 resp := io.vecLoadIssueResp(i)(deqIdx) 282 }) 283 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 284 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 285 } 286 287 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 288 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 289 290 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 291 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 292} 293 294class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 295 extends SchedulerImpBase(wrapper) 296 with HasXSParameter 297{ 298// dontTouch(io.vfWbFuBusyTable) 299 println(s"[SchedulerArithImp] " + 300 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 301 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 302 303 issueQueues.zipWithIndex.foreach { case (iq, i) => 304 iq.io.flush <> io.fromCtrlBlock.flush 305 iq.io.enq <> dispatch2Iq.io.out(i) 306 val intWBIQ = params.schdType match { 307 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 308 case VfScheduler() => wakeupFromVfWBVec 309 case _ => null 310 } 311 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 312 } 313} 314 315// FIXME: Vector mem instructions may not be handled properly! 316class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 317 extends SchedulerImpBase(wrapper) 318 with HasXSParameter 319{ 320 println(s"[SchedulerMemImp] " + 321 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 322 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 323 324 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 325 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 326 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 327 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 328 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 329 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 330 331 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 332 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 333 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 334 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 335 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 336 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 337 338 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 339 340 private val loadWakeUp = issueQueues.filter(_.params.LdExuCnt > 0).map(_.asInstanceOf[IssueQueueMemAddrImp].io.memIO.get.loadWakeUp).flatten 341 require(loadWakeUp.length == io.fromMem.get.wakeup.length) 342 loadWakeUp.zip(io.fromMem.get.wakeup).foreach(x => x._1 := x._2) 343 344 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 345 iq.io.flush <> io.fromCtrlBlock.flush 346 iq.io.enq <> dispatch2Iq.io.out(i) 347 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 348 } 349 350 ldAddrIQs.zipWithIndex.foreach { 351 case (imp: IssueQueueMemAddrImp, i) => 352 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 353 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 354 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 355 case _ => 356 } 357 358 stAddrIQs.zipWithIndex.foreach { 359 case (imp: IssueQueueMemAddrImp, i) => 360 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 361 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 362 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 363 case _ => 364 } 365 366 hyuIQs.zip(hyuIQIdxs).foreach { 367 case (imp: IssueQueueMemAddrImp, idx) => 368 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 369 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 370 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 371 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 372 // TODO: refactor ditry code 373 imp.io.deqDelay(1).ready := false.B 374 io.toDataPathAfterDelay(idx)(1).valid := false.B 375 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 376 case _ => 377 } 378 379 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 380 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 381 382 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 383 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 384 385 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 386 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 387 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 388 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 389 390 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 391 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 392 393 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 394 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 395 396 val d2IqStaOut = dispatch2Iq.io.out.zipWithIndex.filter(staIdxSeq contains _._2).unzip._1.flatten 397 d2IqStaOut.zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 398 val isAllReady = staIQ.ready && stdIQ.ready 399 dp.ready := isAllReady 400 staIQ.valid := dp.valid && isAllReady 401 stdIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 402 } 403 404 val d2IqHyaOut = dispatch2Iq.io.out.zipWithIndex.filter(hyaIdxSeq contains _._2).unzip._1.flatten 405 d2IqHyaOut.zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 406 val isAllReady = hyaIQ.ready && hydIQ.ready 407 dp.ready := isAllReady 408 hyaIQ.valid := dp.valid && isAllReady 409 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 410 } 411 412 stDataIQs.zipWithIndex.foreach { case (iq, i) => 413 iq.io.flush <> io.fromCtrlBlock.flush 414 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 415 } 416 417 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 418 stdIQEnq.bits := staIQEnq.bits 419 // Store data reuses store addr src(1) in dispatch2iq 420 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 421 // \ 422 // ---src*(1)--> [stdIQ] 423 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 424 // instead of dispatch2Iq.io.out(x).bits.src*(1) 425 val stdIdx = 1 426 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 427 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 428 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 429 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 430 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 431 } 432 433 vecMemIQs.foreach { 434 case imp: IssueQueueVecMemImp => 435 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 436 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 437 // not used 438 //imp.io.memIO.get.feedbackIO.head := io.fromMem.get.vstuFeedback.head // only vector store replay 439 // maybe not used 440 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 441 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 442 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 443 444 case _ => 445 } 446 val vecMemFeedbackIO: Seq[MemRSFeedbackIO] = vecMemIQs.map { 447 case imp: IssueQueueVecMemImp => 448 imp.io.memIO.get.feedbackIO 449 }.flatten 450 assert(vecMemFeedbackIO.size == io.fromMem.get.vstuFeedback.size, "vecMemFeedback size dont match!") 451 vecMemFeedbackIO.zip(io.fromMem.get.vstuFeedback).foreach{ 452 case (sink, source) => 453 sink := source 454 } 455 456 val lsqEnqCtrl = Module(new LsqEnqCtrl) 457 458 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 459 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 460 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 461 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 462 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 463 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 464 dispatch2Iq.io.lqFreeCount.get := lsqEnqCtrl.io.lqFreeCount 465 dispatch2Iq.io.sqFreeCount.get := lsqEnqCtrl.io.sqFreeCount 466 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 467 468 dontTouch(io.vecLoadIssueResp) 469} 470