xref: /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala (revision 57c4f8d6c40b210d99a6e8c1f324345547eb16db) 
1package xiangshan.backend.rename
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6
7class Rename extends XSModule with NeedImpl {
8  val io = IO(new Bundle() {
9    val redirect = Flipped(ValidIO(new Redirect))
10    val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
11    val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput)))
12    val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput)))
13    val intPregRdy = Vec(NRReadPorts, Output(Bool()))
14    val fpPregRdy = Vec(NRReadPorts, Output(Bool()))
15    // from decode buffer
16    val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
17    // to dispatch1
18    val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
19  })
20}
21