1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31 32class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 33 34 // params alias 35 private val numRegSrc = backendParams.numRegSrc 36 private val numVecRegSrc = backendParams.numVecRegSrc 37 private val numVecRatPorts = numVecRegSrc 38 39 println(s"[Rename] numRegSrc: $numRegSrc") 40 41 val io = IO(new Bundle() { 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val rabCommits = Input(new RabCommitIO) 44 // from decode 45 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 46 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 47 // ssit read result 48 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 49 // waittable read result 50 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 51 // to rename table 52 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 53 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 54 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 55 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 // from rename table 59 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 60 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 61 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 62 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 63 // to dispatch1 64 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 65 // for snapshots 66 val snpt = Input(new SnapshotPort) 67 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 68 val snptIsFull= Input(Bool()) 69 // debug arch ports 70 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 71 val debug_vconfig_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 72 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 73 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 74 // perf only 75 val stallReason = new Bundle { 76 val in = Flipped(new StallReasonIO(RenameWidth)) 77 val out = new StallReasonIO(RenameWidth) 78 } 79 }) 80 81 val compressUnit = Module(new CompressUnit()) 82 // create free list and rat 83 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 84 val fpFreeList = Module(new StdFreeList(VfPhyRegs - FpLogicRegs - VecLogicRegs)) 85 86 intFreeList.io.commit <> io.rabCommits 87 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 88 fpFreeList.io.commit <> io.rabCommits 89 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 90 91 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 92 // fp and vec share `fpFreeList` 93 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 94 case Reg_I => x.rfWen && x.ldest =/= 0.U 95 case Reg_F => x.fpWen 96 case Reg_V => x.vecWen 97 } 98 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 99 reg_t match { 100 case Reg_I => x.rfWen 101 case Reg_F => x.fpWen 102 case Reg_V => x.vecWen 103 } 104 } 105 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 106 reg_t match { 107 case Reg_I => x.rfWen && x.ldest =/= 0.U 108 case Reg_F => x.fpWen 109 case Reg_V => x.vecWen 110 } 111 } 112 113 // connect [redirect + walk] ports for __float point__ & __integer__ free list 114 Seq(fpFreeList, intFreeList).foreach { case fl => 115 fl.io.redirect := io.redirect.valid 116 fl.io.walk := io.rabCommits.isWalk 117 } 118 // only when both fp and int free list and dispatch1 has enough space can we do allocation 119 // when isWalk, freelist can definitely allocate 120 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.rabCommits.isWalk 121 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.rabCommits.isWalk 122 123 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 124 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.rabCommits.isWalk 125 126 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 127 sink.valid := source.valid 128 sink.bits := source.bits 129 } 130 val needRobFlags = compressUnit.io.out.needRobFlags 131 val instrSizesVec = compressUnit.io.out.instrSizes 132 val compressMasksVec = compressUnit.io.out.masks 133 134 // speculatively assign the instruction with an robIdx 135 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 136 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 137 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 138 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 139 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 140 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 141 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 142 robIdxHead := robIdxHeadNext 143 144 /** 145 * Rename: allocate free physical register and update rename table 146 */ 147 val uops = Wire(Vec(RenameWidth, new DynInst)) 148 uops.foreach( uop => { 149 uop.srcState := DontCare 150 uop.debugInfo := DontCare 151 uop.lqIdx := DontCare 152 uop.sqIdx := DontCare 153 uop.waitForRobIdx := DontCare 154 uop.singleStep := DontCare 155 uop.snapshot := DontCare 156 uop.srcLoadDependency := DontCare 157 }) 158 159 val needVecDest = Wire(Vec(RenameWidth, Bool())) 160 val needFpDest = Wire(Vec(RenameWidth, Bool())) 161 val needIntDest = Wire(Vec(RenameWidth, Bool())) 162 val hasValid = Cat(io.in.map(_.valid)).orR 163 private val inHeadValid = io.in.head.valid 164 165 val isMove = Wire(Vec(RenameWidth, Bool())) 166 isMove zip io.in.map(_.bits) foreach { 167 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 168 } 169 170 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 171 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 172 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 173 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 174 175 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 176 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 177 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 178 179 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 180 181 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 182 183 // uop calculation 184 for (i <- 0 until RenameWidth) { 185 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 186 187 // update cf according to ssit result 188 uops(i).storeSetHit := io.ssit(i).valid 189 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 190 uops(i).ssid := io.ssit(i).ssid 191 192 // update cf according to waittable result 193 uops(i).loadWaitBit := io.waittable(i) 194 195 uops(i).replayInst := false.B // set by IQ or MemQ 196 // alloc a new phy reg, fp and vec share the `fpFreeList` 197 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 198 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 199 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 200 if (i < RabCommitWidth) { 201 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 202 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 203 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 204 walkIsMove(i) := io.rabCommits.info(i).isMove 205 } 206 fpFreeList.io.allocateReq(i) := needFpDest(i) || needVecDest(i) 207 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) || walkNeedVecDest(i) 208 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 209 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 210 211 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 212 io.in(i).ready := !hasValid || canOut 213 214 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 215 uops(i).instrSize := instrSizesVec(i) 216 when(isMove(i)) { 217 uops(i).numUops := 0.U 218 uops(i).numWB := 0.U 219 } 220 if (i > 0) { 221 when(!needRobFlags(i - 1)) { 222 uops(i).firstUop := false.B 223 uops(i).ftqPtr := uops(i - 1).ftqPtr 224 uops(i).ftqOffset := uops(i - 1).ftqOffset 225 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 226 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 227 } 228 } 229 when(!needRobFlags(i)) { 230 uops(i).lastUop := false.B 231 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 232 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 233 } 234 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 235 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 236 237 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 238 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 239 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 240 uops(i).psrc(3) := io.vecReadPorts(i)(3) 241 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 242 243 // int psrc2 should be bypassed from next instruction if it is fused 244 if (i < RenameWidth - 1) { 245 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 246 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 247 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 248 uops(i).psrc(1) := 0.U 249 } 250 } 251 uops(i).eliminatedMove := isMove(i) 252 253 // update pdest 254 uops(i).pdest := MuxCase(0.U, Seq( 255 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 256 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 257 )) 258 259 // Assign performance counters 260 uops(i).debugInfo.renameTime := GTimer() 261 262 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.rabCommits.isWalk 263 io.out(i).bits := uops(i) 264 // Todo: move these shit in decode stage 265 // dirty code for fence. The lsrc is passed by imm. 266 when (io.out(i).bits.fuType === FuType.fence.U) { 267 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 268 } 269 270 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 271// when (io.in(i).bits.isSoftPrefetch) { 272// io.out(i).bits.fuType := FuType.ldu.U 273// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 274// io.out(i).bits.selImm := SelImm.IMM_S 275// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 276// } 277 278 // dirty code for lui+addi(w) fusion 279 if (i < RenameWidth - 1) { 280 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 281 when (fused_lui32) { 282 val lui_imm = io.in(i).bits.imm(19, 0) 283 val add_imm = io.in(i + 1).bits.imm(11, 0) 284 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 285 io.out(i).bits.imm := Cat(lui_imm, add_imm) 286 } 287 } 288 289 // write speculative rename table 290 // we update rat later inside commit code 291 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 292 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 293 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 294 295 296 if (i < RabCommitWidth) { 297 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 298 walkPdest(i) := io.rabCommits.info(i).pdest 299 } else { 300 walkPdest(i) := io.out(i).bits.pdest 301 } 302 } 303 304 /** 305 * How to set psrc: 306 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 307 * - default: psrc from RAT 308 * How to set pdest: 309 * - Mux(isMove, psrc, pdest_from_freelist). 310 * 311 * The critical path of rename lies here: 312 * When move elimination is enabled, we need to update the rat with psrc. 313 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 314 * 315 * If we expand these logic for pdest(N): 316 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 317 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 318 * Mux(bypass(N, N - 2), pdest(N - 2), 319 * ... 320 * Mux(bypass(N, 0), pdest(0), 321 * rat_out(N))...)), 322 * freelist_out(N)) 323 */ 324 // a simple functional model for now 325 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 326 327 // psrc(n) + pdest(1) 328 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 329 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 330 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 331 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 332 for (i <- 1 until RenameWidth) { 333 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 334 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 335 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 336 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 337 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 338 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 339 val indexMatch = in.bits.ldest === t 340 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 341 indexMatch && writeMatch 342 } 343 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 344 } 345 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 346 (z, next) => Mux(next._2, next._1, z) 347 } 348 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 349 (z, next) => Mux(next._2, next._1, z) 350 } 351 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 352 (z, next) => Mux(next._2, next._1, z) 353 } 354 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 355 (z, next) => Mux(next._2, next._1, z) 356 } 357 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 358 (z, next) => Mux(next._2, next._1, z) 359 } 360 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 361 362 // Todo: better implementation for fields reuse 363 // For fused-lui-load, load.src(0) is replaced by the imm. 364 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 365 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 366 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 367 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 368 when (fused_lui_load) { 369 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 370 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 371 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 372 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 373 io.out(i).bits.srcType(0) := SrcType.imm 374 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 375 } 376 377 } 378 379 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 380 val lastCycleCreateSnpt = RegInit(false.B) 381 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 382 val sameSnptDistance = (RobCommitWidth * 4).U 383 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 384 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 385 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 386 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 387 if(backendParams.debugEn){ 388 dontTouch(robIdxHeadNext) 389 dontTouch(notInSameSnpt) 390 dontTouch(genSnapshot) 391 } 392 intFreeList.io.snpt := io.snpt 393 fpFreeList.io.snpt := io.snpt 394 intFreeList.io.snpt.snptEnq := genSnapshot 395 fpFreeList.io.snpt.snptEnq := genSnapshot 396 397 /** 398 * Instructions commit: update freelist and rename table 399 */ 400 for (i <- 0 until RabCommitWidth) { 401 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 402 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 403 404 // I. RAT Update 405 // When redirect happens (mis-prediction), don't update the rename table 406 io.intRenamePorts(i).wen := intSpecWen(i) 407 io.intRenamePorts(i).addr := uops(i).ldest 408 io.intRenamePorts(i).data := io.out(i).bits.pdest 409 410 io.fpRenamePorts(i).wen := fpSpecWen(i) 411 io.fpRenamePorts(i).addr := uops(i).ldest 412 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 413 414 io.vecRenamePorts(i).wen := vecSpecWen(i) 415 io.vecRenamePorts(i).addr := uops(i).ldest 416 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 417 418 // II. Free List Update 419 intFreeList.io.freeReq(i) := io.int_need_free(i) 420 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 421 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && (needDestRegCommit(Reg_F, io.rabCommits.info(i)) || needDestRegCommit(Reg_V, io.rabCommits.info(i)))) 422 fpFreeList.io.freePhyReg(i) := Mux(RegNext(needDestRegCommit(Reg_F, io.rabCommits.info(i))), io.fp_old_pdest(i), io.vec_old_pdest(i)) 423 } 424 425 /* 426 Debug and performance counters 427 */ 428 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 429 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 430 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 431 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 432 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 433 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 434 ) 435 } 436 437 for ((x,y) <- io.in.zip(io.out)) { 438 printRenameInfo(x, y) 439 } 440 441 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 442 // bad speculation 443 val recStall = io.redirect.valid || io.rabCommits.isWalk 444 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 445 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 446 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 447 XSPerfAccumulate("recovery_stall", recStall) 448 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 449 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 450 XSPerfAccumulate("other_recovery_stall", otherRecStall) 451 // freelist stall 452 val notRecStall = !io.out.head.valid && !recStall 453 val intFlStall = notRecStall && inHeadValid && !intFreeList.io.canAllocate 454 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate 455 // other stall 456 val otherStall = notRecStall && !intFlStall && !fpFlStall 457 458 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 459 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 460 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 461 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 462 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 463 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 464 intFlStall -> TopDownCounters.IntFlStall.id.U, 465 fpFlStall -> TopDownCounters.FpFlStall.id.U 466 ) 467 )) 468 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 469 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 470 } 471 472 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 473 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 474 for (i <- 0 until RabCommitWidth) { 475 val info = io.rabCommits.info(i) 476 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 477 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}") 478 } 479 480 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 481 482 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 483 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 484 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 485 XSPerfAccumulate("wait_cycle", !io.in.head.valid && io.out.head.ready) 486 487 // These stall reasons could overlap each other, but we configure the priority as fellows. 488 // walk stall > dispatch stall > int freelist stall > fp freelist stall 489 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 490 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 491 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !io.out(0).ready 492 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate 493 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate 494 XSPerfAccumulate("stall_cycle", inHeadStall) 495 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 496 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 497 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 498 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 499 500 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 501 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 502 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 503 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 504 505 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 506 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 507 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 508 509 val renamePerf = Seq( 510 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 511 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 512 ("rename_stall ", inHeadStall), 513 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 514 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !io.out(0).ready), 515 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate), 516 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 517 ) 518 val intFlPerf = intFreeList.getPerfEvents 519 val fpFlPerf = fpFreeList.getPerfEvents 520 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 521 generatePerfEvent() 522} 523