1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class RenameBypassInfo extends XSBundle { 9 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 10 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 11 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13} 14 15class Rename extends XSModule { 16 val io = IO(new Bundle() { 17 val redirect = Flipped(ValidIO(new Redirect)) 18 val roqCommits = Flipped(new RoqCommitIO) 19 // from decode buffer 20 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 21 // to dispatch1 22 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 23 val renameBypass = Output(new RenameBypassInfo) 24 }) 25 26 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 27 XSInfo( 28 in.valid && in.ready, 29 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 30 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 31 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 32 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 33 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 34 p"old_pdest:${out.bits.old_pdest} " + 35 p"out v:${out.valid} r:${out.ready}\n" 36 ) 37 } 38 39 for((x,y) <- io.in.zip(io.out)){ 40 printRenameInfo(x, y) 41 } 42 43 val fpFreeList, intFreeList = Module(new FreeList).io 44 val fpRat = Module(new RenameTable(float = true)).io 45 val intRat = Module(new RenameTable(float = false)).io 46 47 fpFreeList.redirect := io.redirect 48 intFreeList.redirect := io.redirect 49 50 fpRat.redirect := io.redirect 51 intRat.redirect := io.redirect 52 fpRat.walkWen := io.roqCommits.isWalk 53 intRat.walkWen := io.roqCommits.isWalk 54 55 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 56 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 57 } 58 fpFreeList.walk.valid := io.roqCommits.isWalk 59 intFreeList.walk.valid := io.roqCommits.isWalk 60 fpFreeList.walk.bits := PopCount((0 until CommitWidth).map(i => io.roqCommits.valid(i) && needDestReg(true, io.roqCommits.uop(i)))) 61 intFreeList.walk.bits := PopCount((0 until CommitWidth).map(i => io.roqCommits.valid(i) && needDestReg(false, io.roqCommits.uop(i)))) 62 // walk has higher priority than allocation and thus we don't use isWalk here 63 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 64 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 65 66 val uops = Wire(Vec(RenameWidth, new MicroOp)) 67 68 uops.foreach( uop => { 69// uop.brMask := DontCare 70// uop.brTag := DontCare 71 uop.src1State := DontCare 72 uop.src2State := DontCare 73 uop.src3State := DontCare 74 uop.roqIdx := DontCare 75 uop.diffTestDebugLrScValid := DontCare 76 uop.lqIdx := DontCare 77 uop.sqIdx := DontCare 78 }) 79 80 val needFpDest = Wire(Vec(RenameWidth, Bool())) 81 val needIntDest = Wire(Vec(RenameWidth, Bool())) 82 val hasValid = Cat(io.in.map(_.valid)).orR 83 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 84 for(i <- 0 until RenameWidth) { 85 uops(i).cf := io.in(i).bits.cf 86 uops(i).ctrl := io.in(i).bits.ctrl 87 uops(i).brTag := io.in(i).bits.brTag 88 89 val inValid = io.in(i).valid 90 91 // alloc a new phy reg 92 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 93 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 94 fpFreeList.req.allocReqs(i) := needFpDest(i) 95 intFreeList.req.allocReqs(i) := needIntDest(i) 96 97 io.in(i).ready := !hasValid || canOut 98 99 // do checkpoints when a branch inst come 100 // for(fl <- Seq(fpFreeList, intFreeList)){ 101 // fl.cpReqs(i).valid := inValid 102 // fl.cpReqs(i).bits := io.in(i).bits.brTag 103 // } 104 105 uops(i).pdest := Mux(needIntDest(i), 106 intFreeList.req.pdests(i), 107 Mux( 108 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 109 0.U, fpFreeList.req.pdests(i) 110 ) 111 ) 112 113 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 114 io.out(i).bits := uops(i) 115 116 // write rename table 117 def writeRat(fp: Boolean) = { 118 val rat = if(fp) fpRat else intRat 119 val freeList = if(fp) fpFreeList else intFreeList 120 // speculative inst write 121 val specWen = freeList.req.allocReqs(i) && freeList.req.canAlloc && freeList.req.doAlloc && !io.roqCommits.isWalk 122 // walk back write 123 val commitDestValid = io.roqCommits.valid(i) && needDestReg(fp, io.roqCommits.uop(i)) 124 val walkWen = commitDestValid && io.roqCommits.isWalk 125 126 rat.specWritePorts(i).wen := specWen || walkWen 127 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits.uop(i).ctrl.ldest) 128 rat.specWritePorts(i).wdata := Mux(specWen, freeList.req.pdests(i), io.roqCommits.uop(i).old_pdest) 129 130 XSInfo(walkWen, 131 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits.uop(i).cf.pc)}" + 132 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 133 ) 134 135 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 136 rat.archWritePorts(i).addr := io.roqCommits.uop(i).ctrl.ldest 137 rat.archWritePorts(i).wdata := io.roqCommits.uop(i).pdest 138 139 XSInfo(rat.archWritePorts(i).wen, 140 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 141 p" pdest:${rat.archWritePorts(i).wdata}\n" 142 ) 143 144 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 145 freeList.deallocPregs(i) := io.roqCommits.uop(i).old_pdest 146 147 } 148 149 writeRat(fp = false) 150 writeRat(fp = true) 151 152 // read rename table 153 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 154 val rat = if(fp) fpRat else intRat 155 val srcCnt = lsrcList.size 156 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 157 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 158 for(k <- 0 until srcCnt+1){ 159 val rportIdx = i * (srcCnt+1) + k 160 if(k != srcCnt){ 161 rat.readPorts(rportIdx).addr := lsrcList(k) 162 psrcVec(k) := rat.readPorts(rportIdx).rdata 163 } else { 164 rat.readPorts(rportIdx).addr := ldest 165 old_pdest := rat.readPorts(rportIdx).rdata 166 } 167 } 168 (psrcVec, old_pdest) 169 } 170 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 171 val ldest = uops(i).ctrl.ldest 172 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 173 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 174 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 175 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 176 uops(i).psrc3 := fpPhySrcVec(2) 177 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 178 } 179 180 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 181 // Instead, we determine whether there're some dependences between the valid instructions. 182 for (i <- 1 until RenameWidth) { 183 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 184 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 185 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 186 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 187 }).reverse) 188 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 189 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 190 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 191 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 192 }).reverse) 193 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 194 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 195 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 196 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 197 }).reverse) 198 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 199 val fpMatch = needFpDest(j) && needFpDest(i) 200 val intMatch = needIntDest(j) && needIntDest(i) 201 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 202 }).reverse) 203 } 204} 205