1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.rename.freelist._ 28import xiangshan.mem.mdp._ 29 30class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 31 val io = IO(new Bundle() { 32 val redirect = Flipped(ValidIO(new Redirect)) 33 val robCommits = Input(new RobCommitIO) 34 // from decode 35 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 36 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 37 // ssit read result 38 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 39 // waittable read result 40 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 41 // to rename table 42 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 43 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 44 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 45 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 46 // to dispatch1 47 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 48 // debug arch ports 49 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 50 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 51 // perf only 52 val stallReason = new Bundle { 53 val in = Flipped(new StallReasonIO(RenameWidth)) 54 val out = new StallReasonIO(RenameWidth) 55 } 56 }) 57 58 // create free list and rat 59 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 60 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 61 val fpFreeList = Module(new StdFreeList(NRPhyRegs - 32)) 62 63 intRefCounter.io.commit <> io.robCommits 64 intRefCounter.io.redirect := io.redirect.valid 65 intRefCounter.io.debug_int_rat <> io.debug_int_rat 66 intFreeList.io.commit <> io.robCommits 67 intFreeList.io.debug_rat <> io.debug_int_rat 68 fpFreeList.io.commit <> io.robCommits 69 fpFreeList.io.debug_rat <> io.debug_fp_rat 70 71 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 72 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 73 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 74 } 75 def needDestRegCommit[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 76 if(fp) x.fpWen else x.rfWen 77 } 78 def needDestRegWalk[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 79 if(fp) x.fpWen else x.rfWen && x.ldest =/= 0.U 80 } 81 82 // connect [redirect + walk] ports for __float point__ & __integer__ free list 83 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 84 fl.io.redirect := io.redirect.valid 85 fl.io.walk := io.robCommits.isWalk 86 } 87 // only when both fp and int free list and dispatch1 has enough space can we do allocation 88 // when isWalk, freelist can definitely allocate 89 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 90 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 91 92 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 93 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 94 95 96 // speculatively assign the instruction with an robIdx 97 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 98 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 99 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 100 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 101 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 102 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 103 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 104 robIdxHead := robIdxHeadNext 105 106 /** 107 * Rename: allocate free physical register and update rename table 108 */ 109 val uops = Wire(Vec(RenameWidth, new MicroOp)) 110 uops.foreach( uop => { 111 uop.srcState(0) := DontCare 112 uop.srcState(1) := DontCare 113 uop.srcState(2) := DontCare 114 uop.robIdx := DontCare 115 uop.debugInfo := DontCare 116 uop.lqIdx := DontCare 117 uop.sqIdx := DontCare 118 }) 119 120 require(RenameWidth >= CommitWidth) 121 122 val needFpDest = Wire(Vec(RenameWidth, Bool())) 123 val needIntDest = Wire(Vec(RenameWidth, Bool())) 124 val hasValid = Cat(io.in.map(_.valid)).orR 125 126 val isMove = io.in.map(_.bits.ctrl.isMove) 127 128 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 129 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 130 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 131 132 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 133 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 134 135 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 136 137 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 138 139 // uop calculation 140 for (i <- 0 until RenameWidth) { 141 uops(i).cf := io.in(i).bits.cf 142 uops(i).ctrl := io.in(i).bits.ctrl 143 144 // update cf according to ssit result 145 uops(i).cf.storeSetHit := io.ssit(i).valid 146 uops(i).cf.loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 147 uops(i).cf.ssid := io.ssit(i).ssid 148 149 // update cf according to waittable result 150 uops(i).cf.loadWaitBit := io.waittable(i) 151 152 // alloc a new phy reg 153 needFpDest(i) := io.in(i).valid && needDestReg(fp = true, io.in(i).bits) 154 needIntDest(i) := io.in(i).valid && needDestReg(fp = false, io.in(i).bits) 155 if (i < CommitWidth) { 156 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(fp = true, io.robCommits.info(i)) 157 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(fp = false, io.robCommits.info(i)) 158 walkIsMove(i) := io.robCommits.info(i).isMove 159 } 160 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedFpDest(i), needFpDest(i)) 161 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 162 163 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 164 io.in(i).ready := !hasValid || canOut 165 166 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 167 168 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, io.intReadPorts(i)(0), io.fpReadPorts(i)(0)) 169 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, io.intReadPorts(i)(1), io.fpReadPorts(i)(1)) 170 // int psrc2 should be bypassed from next instruction if it is fused 171 if (i < RenameWidth - 1) { 172 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 173 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 174 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 175 uops(i).psrc(1) := 0.U 176 } 177 } 178 uops(i).psrc(2) := io.fpReadPorts(i)(2) 179 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, io.intReadPorts(i).last, io.fpReadPorts(i).last) 180 uops(i).eliminatedMove := isMove(i) 181 182 // update pdest 183 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 184 // normal fp inst 185 Mux(needFpDest(i), fpFreeList.io.allocatePhyReg(i), 186 /* default */0.U)) 187 188 // Assign performance counters 189 uops(i).debugInfo.renameTime := GTimer() 190 191 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 192 io.out(i).bits := uops(i) 193 // dirty code for fence. The lsrc is passed by imm. 194 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 195 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 196 } 197 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 198 when (io.in(i).bits.ctrl.isSoftPrefetch) { 199 io.out(i).bits.ctrl.fuType := FuType.ldu 200 io.out(i).bits.ctrl.fuOpType := Mux(io.in(i).bits.ctrl.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 201 io.out(i).bits.ctrl.selImm := SelImm.IMM_S 202 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.imm(io.in(i).bits.ctrl.imm.getWidth - 1, 5), 0.U(5.W)) 203 } 204 205 // write speculative rename table 206 // we update rat later inside commit code 207 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 208 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 209 210 if (i < CommitWidth) { 211 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 212 walkPdest(i) := io.robCommits.info(i).pdest 213 } else { 214 walkPdest(i) := io.out(i).bits.pdest 215 } 216 217 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 218 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 219 } 220 221 /** 222 * How to set psrc: 223 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 224 * - default: psrc from RAT 225 * How to set pdest: 226 * - Mux(isMove, psrc, pdest_from_freelist). 227 * 228 * The critical path of rename lies here: 229 * When move elimination is enabled, we need to update the rat with psrc. 230 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 231 * 232 * If we expand these logic for pdest(N): 233 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 234 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 235 * Mux(bypass(N, N - 2), pdest(N - 2), 236 * ... 237 * Mux(bypass(N, 0), pdest(0), 238 * rat_out(N))...)), 239 * freelist_out(N)) 240 */ 241 // a simple functional model for now 242 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 243 val bypassCond = Wire(Vec(4, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 244 for (i <- 1 until RenameWidth) { 245 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 246 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 247 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 248 for ((((cond1, cond2), t), j) <- fpCond.zip(intCond).zip(target).zipWithIndex) { 249 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 250 val indexMatch = in.bits.ctrl.ldest === t 251 val writeMatch = cond2 && needIntDest(j) || cond1 && needFpDest(j) 252 indexMatch && writeMatch 253 } 254 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 255 } 256 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 257 (z, next) => Mux(next._2, next._1, z) 258 } 259 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 260 (z, next) => Mux(next._2, next._1, z) 261 } 262 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 263 (z, next) => Mux(next._2, next._1, z) 264 } 265 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).old_pdest) { 266 (z, next) => Mux(next._2, next._1, z) 267 } 268 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 269 270 // For fused-lui-load, load.src(0) is replaced by the imm. 271 val last_is_lui = io.in(i - 1).bits.ctrl.selImm === SelImm.IMM_U && io.in(i - 1).bits.ctrl.srcType(0) =/= SrcType.pc 272 val this_is_load = io.in(i).bits.ctrl.fuType === FuType.ldu 273 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 274 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 275 when (fused_lui_load) { 276 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 277 val lui_imm = io.in(i - 1).bits.ctrl.imm 278 val ld_imm = io.in(i).bits.ctrl.imm 279 io.out(i).bits.ctrl.srcType(0) := SrcType.imm 280 io.out(i).bits.ctrl.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 281 val psrcWidth = uops(i).psrc.head.getWidth 282 val lui_imm_in_imm = uops(i).ctrl.imm.getWidth - Imm_I().len 283 val left_lui_imm = Imm_U().len - lui_imm_in_imm 284 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 285 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 286 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 287 } 288 289 } 290 291 /** 292 * Instructions commit: update freelist and rename table 293 */ 294 for (i <- 0 until CommitWidth) { 295 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 296 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 297 298 Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) => 299 /* 300 I. RAT Update 301 */ 302 303 // walk back write - restore spec state : ldest => old_pdest 304 if (fp && i < RenameWidth) { 305 // When redirect happens (mis-prediction), don't update the rename table 306 rat(i).wen := fpSpecWen(i) 307 rat(i).addr := uops(i).ctrl.ldest 308 rat(i).data := fpFreeList.io.allocatePhyReg(i) 309 } else if (!fp && i < RenameWidth) { 310 rat(i).wen := intSpecWen(i) 311 rat(i).addr := uops(i).ctrl.ldest 312 rat(i).data := io.out(i).bits.pdest 313 } 314 315 /* 316 II. Free List Update 317 */ 318 if (fp) { // Float Point free list 319 fpFreeList.io.freeReq(i) := commitValid && needDestRegCommit(fp, io.robCommits.info(i)) 320 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 321 } else { // Integer free list 322 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 323 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 324 } 325 } 326 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(false, io.robCommits.info(i)) && !io.robCommits.isWalk 327 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 328 } 329 330 when(io.robCommits.isWalk) { 331 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 332 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 333 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 334 } 335 } 336 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 337 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 338 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 339 } 340 } 341 } 342 343 /* 344 Debug and performance counters 345 */ 346 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 347 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 348 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 349 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 350 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 351 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 352 p"old_pdest:${out.bits.old_pdest}\n" 353 ) 354 } 355 356 for((x,y) <- io.in.zip(io.out)){ 357 printRenameInfo(x, y) 358 } 359 360 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 361 // bad speculation 362 val recStall = io.redirect.valid || io.robCommits.isWalk 363 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.robCommits.isWalk && debugRedirect.debugIsCtrl) 364 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.robCommits.isWalk && debugRedirect.debugIsMemVio) 365 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 366 XSPerfAccumulate("recovery_stall", recStall) 367 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 368 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 369 XSPerfAccumulate("other_recovery_stall", otherRecStall) 370 // freelist stall 371 val notRecStall = !io.out.head.valid && !recStall 372 val intFlStall = notRecStall && hasValid && !intFreeList.io.canAllocate 373 val fpFlStall = notRecStall && hasValid && !fpFreeList.io.canAllocate 374 // other stall 375 val otherStall = notRecStall && !intFlStall && !fpFlStall 376 377 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 378 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 379 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 380 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 381 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 382 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 383 intFlStall -> TopDownCounters.IntFlStall.id.U, 384 fpFlStall -> TopDownCounters.FpFlStall.id.U 385 ) 386 )) 387 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 388 out := Mux(io.stallReason.in.backReason.valid, 389 io.stallReason.in.backReason.bits, 390 Mux(valid, TopDownCounters.NoStall.id.U, in)) 391 } 392 393 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 394 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 395 for (i <- 0 until CommitWidth) { 396 val info = io.robCommits.info(i) 397 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 398 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + 399 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 400 } 401 402 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 403 404 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 405 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 406 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 407 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 408 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 409 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 410 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 411 412 XSPerfHistogram("slots_fire", PopCount(io.out.map(_.fire)), true.B, 0, RenameWidth+1, 1) 413 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 414 XSPerfHistogram("slots_valid_pure", PopCount(io.in.map(_.valid)), io.out(0).fire, 0, RenameWidth+1, 1) 415 XSPerfHistogram("slots_valid_rough", PopCount(io.in.map(_.valid)), true.B, 0, RenameWidth+1, 1) 416 417 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.ctrl.isMove))) 418 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm) 419 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 420 421 422 val renamePerf = Seq( 423 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 424 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 425 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 426 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 427 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 428 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 429 ) 430 val intFlPerf = intFreeList.getPerfEvents 431 val fpFlPerf = fpFreeList.getPerfEvents 432 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 433 generatePerfEvent() 434} 435