1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import xiangshan.backend.roq.RoqPtr 8import xiangshan.backend.dispatch.PreDispatchInfo 9 10class RenameBypassInfo extends XSBundle { 11 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 14 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 15} 16 17class Rename extends XSModule with HasCircularQueuePtrHelper { 18 val io = IO(new Bundle() { 19 val redirect = Flipped(ValidIO(new Redirect)) 20 val flush = Input(Bool()) 21 val roqCommits = Flipped(new RoqCommitIO) 22 // from decode buffer 23 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 24 // to dispatch1 25 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 26 val renameBypass = Output(new RenameBypassInfo) 27 val dispatchInfo = Output(new PreDispatchInfo) 28 }) 29 30 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 31 XSInfo( 32 in.valid && in.ready, 33 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 34 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 35 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 36 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 37 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 38 p"old_pdest:${out.bits.old_pdest} " + 39 p"out v:${out.valid} r:${out.ready}\n" 40 ) 41 } 42 43 for((x,y) <- io.in.zip(io.out)){ 44 printRenameInfo(x, y) 45 } 46 47 val intFreeList, fpFreeList = Module(new FreeList).io 48 val intRat = Module(new RenameTable(float = false)).io 49 val fpRat = Module(new RenameTable(float = true)).io 50 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 51 52 allPhyResource.map{ case (rat, freelist, _) => 53 rat.redirect := io.redirect.valid 54 rat.flush := io.flush 55 rat.walkWen := io.roqCommits.isWalk 56 freelist.redirect := io.redirect.valid 57 freelist.flush := io.flush 58 freelist.walk.valid := io.roqCommits.isWalk 59 } 60 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 61 62 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 63 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 64 } 65 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 66 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 67 } 68 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 69 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 70 // walk has higher priority than allocation and thus we don't use isWalk here 71 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 72 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 73 74 // speculatively assign the instruction with an roqIdx 75 val validCount = PopCount(io.in.map(_.valid)) 76 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 77 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 78 val roqIdxHeadNext = Mux(io.flush, 79 0.U.asTypeOf(new RoqPtr), 80 Mux(io.redirect.valid, 81 io.redirect.bits.roqIdx, 82 Mux(lastCycleMisprediction, 83 roqIdxHead + 1.U, 84 Mux(canOut, roqIdxHead + validCount, roqIdxHead)) 85 ) 86 ) 87 roqIdxHead := roqIdxHeadNext 88 89 /** 90 * Rename: allocate free physical register and update rename table 91 */ 92 val uops = Wire(Vec(RenameWidth, new MicroOp)) 93 94 uops.foreach( uop => { 95// uop.brMask := DontCare 96// uop.brTag := DontCare 97 uop.src1State := DontCare 98 uop.src2State := DontCare 99 uop.src3State := DontCare 100 uop.roqIdx := DontCare 101 uop.diffTestDebugLrScValid := DontCare 102 uop.debugInfo := DontCare 103 uop.lqIdx := DontCare 104 uop.sqIdx := DontCare 105 }) 106 107 val needFpDest = Wire(Vec(RenameWidth, Bool())) 108 val needIntDest = Wire(Vec(RenameWidth, Bool())) 109 val hasValid = Cat(io.in.map(_.valid)).orR 110 for (i <- 0 until RenameWidth) { 111 uops(i).cf := io.in(i).bits.cf 112 uops(i).ctrl := io.in(i).bits.ctrl 113 114 val inValid = io.in(i).valid 115 116 // alloc a new phy reg 117 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 118 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 119 fpFreeList.req.allocReqs(i) := needFpDest(i) 120 intFreeList.req.allocReqs(i) := needIntDest(i) 121 122 io.in(i).ready := !hasValid || canOut 123 124 // do checkpoints when a branch inst come 125 // for(fl <- Seq(fpFreeList, intFreeList)){ 126 // fl.cpReqs(i).valid := inValid 127 // fl.cpReqs(i).bits := io.in(i).bits.brTag 128 // } 129 130 uops(i).pdest := Mux(needIntDest(i), 131 intFreeList.req.pdests(i), 132 Mux( 133 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 134 0.U, fpFreeList.req.pdests(i) 135 ) 136 ) 137 138 uops(i).roqIdx := roqIdxHead + i.U 139 140 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 141 io.out(i).bits := uops(i) 142 143 // write speculative rename table 144 allPhyResource.map{ case (rat, freelist, _) => 145 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 146 147 rat.specWritePorts(i).wen := specWen 148 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 149 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 150 151 freelist.deallocReqs(i) := specWen 152 } 153 154 // read rename table 155 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 156 val rat = if(fp) fpRat else intRat 157 val srcCnt = lsrcList.size 158 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 159 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 160 for(k <- 0 until srcCnt+1){ 161 val rportIdx = i * (srcCnt+1) + k 162 if(k != srcCnt){ 163 rat.readPorts(rportIdx).addr := lsrcList(k) 164 psrcVec(k) := rat.readPorts(rportIdx).rdata 165 } else { 166 rat.readPorts(rportIdx).addr := ldest 167 old_pdest := rat.readPorts(rportIdx).rdata 168 } 169 } 170 (psrcVec, old_pdest) 171 } 172 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 173 val ldest = uops(i).ctrl.ldest 174 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 175 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 176 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 177 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 178 uops(i).psrc3 := fpPhySrcVec(2) 179 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 180 } 181 182 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 183 // Instead, we determine whether there're some dependences between the valid instructions. 184 for (i <- 1 until RenameWidth) { 185 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 186 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 187 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 188 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 189 }).reverse) 190 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 191 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 192 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 193 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 194 }).reverse) 195 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 196 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 197 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 198 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 199 }).reverse) 200 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 201 val fpMatch = needFpDest(j) && needFpDest(i) 202 val intMatch = needIntDest(j) && needIntDest(i) 203 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 204 }).reverse) 205 } 206 207 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 208 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 209 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 210 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 211 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 212 213 /** 214 * Instructions commit: update freelist and rename table 215 */ 216 for (i <- 0 until CommitWidth) { 217 if (i >= RenameWidth) { 218 allPhyResource.map{ case (rat, _, _) => 219 rat.specWritePorts(i).wen := false.B 220 rat.specWritePorts(i).addr := DontCare 221 rat.specWritePorts(i).wdata := DontCare 222 } 223 } 224 225 allPhyResource.map{ case (rat, freelist, fp) => 226 // walk back write 227 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 228 229 when (commitDestValid && io.roqCommits.isWalk) { 230 rat.specWritePorts(i).wen := true.B 231 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 232 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 233 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 234 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 235 } 236 237 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 238 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 239 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 240 241 XSInfo(rat.archWritePorts(i).wen, 242 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 243 p" pdest:${rat.archWritePorts(i).wdata}\n" 244 ) 245 246 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 247 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 248 } 249 } 250 251 XSPerf("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 252 XSPerf("utilization", PopCount(io.in.map(_.valid))) 253 XSPerf("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 254 XSPerf("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 255 XSPerf("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 256 XSPerf("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && !intFreeList.req.canAlloc && !io.roqCommits.isWalk) 257 XSPerf("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && io.roqCommits.isWalk) 258 259} 260