1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class RenameBypassInfo extends XSBundle { 9 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 10 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 11 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13} 14 15class Rename extends XSModule { 16 val io = IO(new Bundle() { 17 val redirect = Flipped(ValidIO(new Redirect)) 18 val roqCommits = Flipped(new RoqCommitIO) 19 // from decode buffer 20 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 21 // to dispatch1 22 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 23 val renameBypass = Output(new RenameBypassInfo) 24 }) 25 26 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 27 XSInfo( 28 in.valid && in.ready, 29 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 30 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 31 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 32 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 33 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 34 p"old_pdest:${out.bits.old_pdest} " + 35 p"out v:${out.valid} r:${out.ready}\n" 36 ) 37 } 38 39 for((x,y) <- io.in.zip(io.out)){ 40 printRenameInfo(x, y) 41 } 42 43 val fpFreeList, intFreeList = Module(new FreeList).io 44 val fpRat = Module(new RenameTable(float = true)).io 45 val intRat = Module(new RenameTable(float = false)).io 46 47 fpFreeList.redirect := io.redirect 48 intFreeList.redirect := io.redirect 49 50 fpRat.redirect := io.redirect 51 intRat.redirect := io.redirect 52 fpRat.walkWen := io.roqCommits.isWalk 53 intRat.walkWen := io.roqCommits.isWalk 54 55 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 56 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 57 } 58 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 59 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 60 } 61 fpFreeList.walk.valid := io.roqCommits.isWalk 62 intFreeList.walk.valid := io.roqCommits.isWalk 63 fpFreeList.walk.bits := PopCount((0 until CommitWidth).map(i => io.roqCommits.valid(i) && needDestRegCommit(true, io.roqCommits.info(i)))) 64 intFreeList.walk.bits := PopCount((0 until CommitWidth).map(i => io.roqCommits.valid(i) && needDestRegCommit(false, io.roqCommits.info(i)))) 65 // walk has higher priority than allocation and thus we don't use isWalk here 66 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 67 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 68 69 val uops = Wire(Vec(RenameWidth, new MicroOp)) 70 71 uops.foreach( uop => { 72// uop.brMask := DontCare 73// uop.brTag := DontCare 74 uop.src1State := DontCare 75 uop.src2State := DontCare 76 uop.src3State := DontCare 77 uop.roqIdx := DontCare 78 uop.diffTestDebugLrScValid := DontCare 79 uop.lqIdx := DontCare 80 uop.sqIdx := DontCare 81 }) 82 83 val needFpDest = Wire(Vec(RenameWidth, Bool())) 84 val needIntDest = Wire(Vec(RenameWidth, Bool())) 85 val hasValid = Cat(io.in.map(_.valid)).orR 86 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 87 for(i <- 0 until RenameWidth) { 88 uops(i).cf := io.in(i).bits.cf 89 uops(i).ctrl := io.in(i).bits.ctrl 90 uops(i).brTag := io.in(i).bits.brTag 91 92 val inValid = io.in(i).valid 93 94 // alloc a new phy reg 95 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 96 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 97 fpFreeList.req.allocReqs(i) := needFpDest(i) 98 intFreeList.req.allocReqs(i) := needIntDest(i) 99 100 io.in(i).ready := !hasValid || canOut 101 102 // do checkpoints when a branch inst come 103 // for(fl <- Seq(fpFreeList, intFreeList)){ 104 // fl.cpReqs(i).valid := inValid 105 // fl.cpReqs(i).bits := io.in(i).bits.brTag 106 // } 107 108 uops(i).pdest := Mux(needIntDest(i), 109 intFreeList.req.pdests(i), 110 Mux( 111 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 112 0.U, fpFreeList.req.pdests(i) 113 ) 114 ) 115 116 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 117 io.out(i).bits := uops(i) 118 119 // write rename table 120 def writeRat(fp: Boolean) = { 121 val rat = if(fp) fpRat else intRat 122 val freeList = if(fp) fpFreeList else intFreeList 123 // speculative inst write 124 val specWen = freeList.req.allocReqs(i) && freeList.req.canAlloc && freeList.req.doAlloc && !io.roqCommits.isWalk 125 // walk back write 126 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 127 val walkWen = commitDestValid && io.roqCommits.isWalk 128 129 rat.specWritePorts(i).wen := specWen || walkWen 130 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits.info(i).ldest) 131 rat.specWritePorts(i).wdata := Mux(specWen, freeList.req.pdests(i), io.roqCommits.info(i).old_pdest) 132 133 XSInfo(walkWen, 134 {if(fp) p"fp" else p"int "} + p"walk: " + 135 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 136 ) 137 138 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 139 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 140 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 141 142 XSInfo(rat.archWritePorts(i).wen, 143 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 144 p" pdest:${rat.archWritePorts(i).wdata}\n" 145 ) 146 147 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 148 freeList.deallocPregs(i) := io.roqCommits.info(i).old_pdest 149 150 } 151 152 writeRat(fp = false) 153 writeRat(fp = true) 154 155 // read rename table 156 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 157 val rat = if(fp) fpRat else intRat 158 val srcCnt = lsrcList.size 159 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 160 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 161 for(k <- 0 until srcCnt+1){ 162 val rportIdx = i * (srcCnt+1) + k 163 if(k != srcCnt){ 164 rat.readPorts(rportIdx).addr := lsrcList(k) 165 psrcVec(k) := rat.readPorts(rportIdx).rdata 166 } else { 167 rat.readPorts(rportIdx).addr := ldest 168 old_pdest := rat.readPorts(rportIdx).rdata 169 } 170 } 171 (psrcVec, old_pdest) 172 } 173 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 174 val ldest = uops(i).ctrl.ldest 175 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 176 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 177 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 178 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 179 uops(i).psrc3 := fpPhySrcVec(2) 180 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 181 } 182 183 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 184 // Instead, we determine whether there're some dependences between the valid instructions. 185 for (i <- 1 until RenameWidth) { 186 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 187 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 188 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 189 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 190 }).reverse) 191 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 192 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 193 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 194 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 195 }).reverse) 196 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 197 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 198 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 199 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 200 }).reverse) 201 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 202 val fpMatch = needFpDest(j) && needFpDest(i) 203 val intMatch = needIntDest(j) && needIntDest(i) 204 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 205 }).reverse) 206 } 207} 208