1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.rename.freelist._ 27import xiangshan.mem.mdp._ 28 29class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents { 30 val io = IO(new Bundle() { 31 val redirect = Flipped(ValidIO(new Redirect)) 32 val robCommits = Flipped(new RobCommitIO) 33 // from decode 34 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 35 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 36 // ssit read result 37 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 38 // waittable read result 39 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 40 // to rename table 41 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 42 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 43 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 44 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 45 // to dispatch1 46 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 47 }) 48 49 // create free list and rat 50 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 51 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 52 val fpFreeList = Module(new StdFreeList(NRPhyRegs - 32)) 53 54 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 55 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 56 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 57 } 58 def needDestRegCommit[T <: RobCommitInfo](fp: Boolean, x: T): Bool = { 59 if(fp) x.fpWen else x.rfWen 60 } 61 62 // connect [redirect + walk] ports for __float point__ & __integer__ free list 63 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 64 fl.io.redirect := io.redirect.valid 65 fl.io.walk := io.robCommits.isWalk 66 // when isWalk, use stepBack to restore head pointer of free list 67 // (if ME enabled, stepBack of intFreeList should be useless thus optimized out) 68 fl.io.stepBack := PopCount(io.robCommits.walkValid.zip(io.robCommits.info).map{case (v, i) => v && needDestRegCommit(isFp, i)}) 69 } 70 // walk has higher priority than allocation and thus we don't use isWalk here 71 // only when both fp and int free list and dispatch1 has enough space can we do allocation 72 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready 73 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready 74 75 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 76 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 77 78 79 // speculatively assign the instruction with an robIdx 80 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter rob (from decode) 81 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 82 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 83 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 84 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 85 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 86 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 87 robIdxHead := robIdxHeadNext 88 89 /** 90 * Rename: allocate free physical register and update rename table 91 */ 92 val uops = Wire(Vec(RenameWidth, new MicroOp)) 93 uops.foreach( uop => { 94 uop.srcState(0) := DontCare 95 uop.srcState(1) := DontCare 96 uop.srcState(2) := DontCare 97 uop.robIdx := DontCare 98 uop.debugInfo := DontCare 99 uop.lqIdx := DontCare 100 uop.sqIdx := DontCare 101 }) 102 103 val needFpDest = Wire(Vec(RenameWidth, Bool())) 104 val needIntDest = Wire(Vec(RenameWidth, Bool())) 105 val hasValid = Cat(io.in.map(_.valid)).orR 106 107 val isMove = io.in.map(_.bits.ctrl.isMove) 108 109 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 110 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 111 112 // uop calculation 113 for (i <- 0 until RenameWidth) { 114 uops(i).cf := io.in(i).bits.cf 115 uops(i).ctrl := io.in(i).bits.ctrl 116 117 // update cf according to ssit result 118 uops(i).cf.storeSetHit := io.ssit(i).valid 119 uops(i).cf.loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 120 uops(i).cf.ssid := io.ssit(i).ssid 121 122 // update cf according to waittable result 123 uops(i).cf.loadWaitBit := io.waittable(i) 124 125 // alloc a new phy reg 126 needFpDest(i) := io.in(i).valid && needDestReg(fp = true, io.in(i).bits) 127 needIntDest(i) := io.in(i).valid && needDestReg(fp = false, io.in(i).bits) 128 fpFreeList.io.allocateReq(i) := needFpDest(i) 129 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 130 131 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 132 io.in(i).ready := !hasValid || canOut 133 134 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(_.valid)) 135 136 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, io.intReadPorts(i)(0), io.fpReadPorts(i)(0)) 137 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, io.intReadPorts(i)(1), io.fpReadPorts(i)(1)) 138 // int psrc2 should be bypassed from next instruction if it is fused 139 if (i < RenameWidth - 1) { 140 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 141 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 142 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 143 uops(i).psrc(1) := 0.U 144 } 145 } 146 uops(i).psrc(2) := io.fpReadPorts(i)(2) 147 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, io.intReadPorts(i).last, io.fpReadPorts(i).last) 148 uops(i).eliminatedMove := isMove(i) 149 150 // update pdest 151 uops(i).pdest := Mux(needIntDest(i), intFreeList.io.allocatePhyReg(i), // normal int inst 152 // normal fp inst 153 Mux(needFpDest(i), fpFreeList.io.allocatePhyReg(i), 154 /* default */0.U)) 155 156 // Assign performance counters 157 uops(i).debugInfo.renameTime := GTimer() 158 159 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 160 io.out(i).bits := uops(i) 161 // dirty code for fence. The lsrc is passed by imm. 162 when (io.out(i).bits.ctrl.fuType === FuType.fence) { 163 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0)) 164 } 165 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 166 when (io.in(i).bits.ctrl.isSoftPrefetch) { 167 io.out(i).bits.ctrl.fuType := FuType.ldu 168 io.out(i).bits.ctrl.fuOpType := Mux(io.in(i).bits.ctrl.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 169 io.out(i).bits.ctrl.selImm := SelImm.IMM_S 170 io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.imm(io.in(i).bits.ctrl.imm.getWidth - 1, 5), 0.U(5.W)) 171 } 172 173 // write speculative rename table 174 // we update rat later inside commit code 175 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 176 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 177 178 intRefCounter.io.allocate(i).valid := intSpecWen(i) 179 intRefCounter.io.allocate(i).bits := io.out(i).bits.pdest 180 } 181 182 /** 183 * How to set psrc: 184 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 185 * - default: psrc from RAT 186 * How to set pdest: 187 * - Mux(isMove, psrc, pdest_from_freelist). 188 * 189 * The critical path of rename lies here: 190 * When move elimination is enabled, we need to update the rat with psrc. 191 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 192 * 193 * If we expand these logic for pdest(N): 194 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 195 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 196 * Mux(bypass(N, N - 2), pdest(N - 2), 197 * ... 198 * Mux(bypass(N, 0), pdest(0), 199 * rat_out(N))...)), 200 * freelist_out(N)) 201 */ 202 // a simple functional model for now 203 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 204 val bypassCond = Wire(Vec(4, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 205 for (i <- 1 until RenameWidth) { 206 val fpCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 207 val intCond = io.in(i).bits.ctrl.srcType.map(_ === SrcType.reg) :+ needIntDest(i) 208 val target = io.in(i).bits.ctrl.lsrc :+ io.in(i).bits.ctrl.ldest 209 for ((((cond1, cond2), t), j) <- fpCond.zip(intCond).zip(target).zipWithIndex) { 210 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 211 val indexMatch = in.bits.ctrl.ldest === t 212 val writeMatch = cond2 && needIntDest(j) || cond1 && needFpDest(j) 213 indexMatch && writeMatch 214 } 215 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 216 } 217 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 218 (z, next) => Mux(next._2, next._1, z) 219 } 220 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 221 (z, next) => Mux(next._2, next._1, z) 222 } 223 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 224 (z, next) => Mux(next._2, next._1, z) 225 } 226 io.out(i).bits.old_pdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).old_pdest) { 227 (z, next) => Mux(next._2, next._1, z) 228 } 229 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 230 231 // For fused-lui-load, load.src(0) is replaced by the imm. 232 val last_is_lui = io.in(i - 1).bits.ctrl.selImm === SelImm.IMM_U && io.in(i - 1).bits.ctrl.srcType(0) =/= SrcType.pc 233 val this_is_load = io.in(i).bits.ctrl.fuType === FuType.ldu 234 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 235 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 236 when (fused_lui_load) { 237 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 238 val lui_imm = io.in(i - 1).bits.ctrl.imm 239 val ld_imm = io.in(i).bits.ctrl.imm 240 io.out(i).bits.ctrl.srcType(0) := SrcType.imm 241 io.out(i).bits.ctrl.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 242 val psrcWidth = uops(i).psrc.head.getWidth 243 val lui_imm_in_imm = uops(i).ctrl.imm.getWidth - Imm_I().len 244 val left_lui_imm = Imm_U().len - lui_imm_in_imm 245 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 246 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 247 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 248 } 249 250 } 251 252 /** 253 * Instructions commit: update freelist and rename table 254 */ 255 for (i <- 0 until CommitWidth) { 256 257 Seq((io.intRenamePorts, false), (io.fpRenamePorts, true)) foreach { case (rat, fp) => 258 // is valid commit req and given instruction has destination register 259 val commitDestValid = io.robCommits.valid(i) && needDestRegCommit(fp, io.robCommits.info(i)) 260 XSDebug(p"isFp[${fp}]index[$i]-commitDestValid:$commitDestValid,isWalk:${io.robCommits.isWalk}\n") 261 262 /* 263 I. RAT Update 264 */ 265 266 // walk back write - restore spec state : ldest => old_pdest 267 if (fp && i < RenameWidth) { 268 // When redirect happens (mis-prediction), don't update the rename table 269 rat(i).wen := fpSpecWen(i) 270 rat(i).addr := uops(i).ctrl.ldest 271 rat(i).data := fpFreeList.io.allocatePhyReg(i) 272 } else if (!fp && i < RenameWidth) { 273 rat(i).wen := intSpecWen(i) 274 rat(i).addr := uops(i).ctrl.ldest 275 rat(i).data := io.out(i).bits.pdest 276 } 277 278 /* 279 II. Free List Update 280 */ 281 if (fp) { // Float Point free list 282 fpFreeList.io.freeReq(i) := commitDestValid && !io.robCommits.isWalk 283 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 284 } else { // Integer free list 285 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 286 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 287 } 288 } 289 intRefCounter.io.deallocate(i).valid := io.robCommits.valid(i) && needDestRegCommit(false, io.robCommits.info(i)) 290 intRefCounter.io.deallocate(i).bits := Mux(io.robCommits.isWalk, io.robCommits.info(i).pdest, io.robCommits.info(i).old_pdest) 291 } 292 293 /* 294 Debug and performance counters 295 */ 296 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 297 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.cf.pc)} in(${in.valid},${in.ready}) " + 298 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 299 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 300 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 301 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 302 p"old_pdest:${out.bits.old_pdest}\n" 303 ) 304 } 305 306 for((x,y) <- io.in.zip(io.out)){ 307 printRenameInfo(x, y) 308 } 309 310 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 311 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.valid.asUInt)}\n") 312 for (i <- 0 until CommitWidth) { 313 val info = io.robCommits.info(i) 314 XSDebug(io.robCommits.isWalk && io.robCommits.valid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 315 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + 316 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 317 } 318 319 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 320 321 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 322 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 323 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 324 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 325 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 326 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 327 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 328 329 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.ctrl.isMove))) 330 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm) 331 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 332 333 334 val renamePerf = Seq( 335 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 336 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 337 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 338 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 339 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 340 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 341 ) 342 val intFlPerf = intFreeList.getPerfEvents 343 val fpFlPerf = fpFreeList.getPerfEvents 344 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 345 generatePerfEvent() 346} 347