xref: /XiangShan/src/main/scala/xiangshan/backend/rob/RobEnqPtrWrapper.scala (revision 780712aa4d2ede8944b843c01f0a3ac94679530e)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ***************************************************************************************/
16
17package xiangshan.backend.rob
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import difftest._
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utility._
25import utils._
26import xiangshan._
27import xiangshan.backend.BackendParams
28import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
29import xiangshan.backend.fu.{FuConfig, FuType}
30import xiangshan.frontend.FtqPtr
31import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr}
32import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
33import xiangshan.backend.ctrlblock.{DebugLSIO, DebugLsInfo, LsTopdownInfo}
34import xiangshan.backend.fu.vector.Bundles.VType
35import xiangshan.backend.rename.SnapshotGenerator
36
37class RobEnqPtrWrapper(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
38  val io = IO(new Bundle {
39    // for input redirect
40    val redirect = Input(Valid(new Redirect))
41    // for enqueue
42    val allowEnqueue = Input(Bool())
43    val hasBlockBackward = Input(Bool())
44    val enq = Vec(RenameWidth, Input(Bool()))
45    val out = Output(Vec(RenameWidth, new RobPtr))
46  })
47
48  val enqPtrVec = RegInit(VecInit.tabulate(RenameWidth)(_.U.asTypeOf(new RobPtr)))
49
50  // enqueue
51  val canAccept = io.allowEnqueue && !io.hasBlockBackward
52  val dispatchNum = Mux(canAccept, PopCount(io.enq), 0.U)
53
54  for ((ptr, i) <- enqPtrVec.zipWithIndex) {
55    when(io.redirect.valid) {
56      ptr := Mux(io.redirect.bits.flushItself(), io.redirect.bits.robIdx + i.U, io.redirect.bits.robIdx + (i + 1).U)
57    }.otherwise {
58      ptr := ptr + dispatchNum
59    }
60  }
61
62  io.out := enqPtrVec
63
64}