1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut} 24import utility.{Code, ParallelOR, ReplacementPolicy, SRAMTemplate, XSDebug} 25import xiangshan.L1CacheErrorInfo 26 27import scala.math.max 28 29 30class L1DataReadReq(implicit p: Parameters) extends DCacheBundle { 31 // you can choose which bank to read to save power 32 val rmask = Bits(blockRows.W) 33 val way_en = Bits(nWays.W) 34 val addr = Bits(untagBits.W) 35} 36 37// Now, we can write a cache-block in a single cycle 38class L1DataWriteReq(implicit p: Parameters) extends L1DataReadReq { 39 val wmask = Bits(blockRows.W) 40 val data = Vec(blockRows, Bits(rowBits.W)) 41} 42 43abstract class AbstractDataArray(implicit p: Parameters) extends DCacheModule { 44 val io = IO(new DCacheBundle { 45 val read = Vec(3, Flipped(DecoupledIO(new L1DataReadReq))) 46 val write = Flipped(DecoupledIO(new L1DataWriteReq)) 47 val resp = Output(Vec(3, Vec(blockRows, Bits(encRowBits.W)))) 48 val nacks = Output(Vec(3, Bool())) 49 val errors = Output(Vec(3, ValidIO(new L1CacheErrorInfo))) 50 }) 51 52 def pipeMap[T <: Data](f: Int => T) = VecInit((0 until 3).map(f)) 53 54 def dumpRead = { 55 (0 until 3) map { w => 56 XSDebug(io.read(w).valid, 57 s"DataArray Read channel: $w valid way_en: %x addr: %x\n", 58 io.read(w).bits.way_en, io.read(w).bits.addr) 59 } 60 } 61 62 def dumpWrite = { 63 XSDebug(io.write.valid, 64 s"DataArray Write valid way_en: %x addr: %x\n", 65 io.write.bits.way_en, io.write.bits.addr) 66 67 (0 until blockRows) map { r => 68 XSDebug(io.write.valid, 69 s"cycle: $r data: %x wmask: %x\n", 70 io.write.bits.data(r), io.write.bits.wmask(r)) 71 } 72 } 73 74 def dumpResp = { 75 (0 until 3) map { w => 76 XSDebug(s"DataArray ReadResp channel: $w\n") 77 (0 until blockRows) map { r => 78 XSDebug(s"cycle: $r data: %x\n", io.resp(w)(r)) 79 } 80 } 81 } 82 83 def dumpNack = { 84 (0 until 3) map { w => 85 XSDebug(io.nacks(w), s"DataArray NACK channel: $w\n") 86 } 87 } 88 89 def dump() = { 90 dumpRead 91 dumpWrite 92 dumpNack 93 dumpResp 94 } 95} 96