1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30 31case class TLBParameters 32( 33 name: String = "none", 34 fetchi: Boolean = false, // TODO: remove it 35 fenceDelay: Int = 2, 36 useDmode: Boolean = true, 37 NSets: Int = 1, 38 NWays: Int = 2, 39 Replacer: Option[String] = Some("plru"), 40 Associative: String = "fa", // must be fa 41 outReplace: Boolean = false, 42 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 43 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 44 saveLevel: Boolean = false, 45 lgMaxSize: Int = 3 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l3 52 l3Size: Int = 16, 53 l3Associative: String = "fa", 54 l3Replacer: Option[String] = Some("plru"), 55 // l2 56 l2Size: Int = 16, 57 l2Associative: String = "fa", 58 l2Replacer: Option[String] = Some("plru"), 59 // l1 60 l1nSets: Int = 8, 61 l1nWays: Int = 2, 62 l1ReservedBits: Int = 10, 63 l1Replacer: Option[String] = Some("setplru"), 64 // l0 65 l0nSets: Int = 32, 66 l0nWays: Int = 4, 67 l0ReservedBits: Int = 3, 68 l0Replacer: Option[String] = Some("setplru"), 69 // sp 70 spSize: Int = 16, 71 spReplacer: Option[String] = Some("plru"), 72 // hash asid width 73 hashAsidWidth: Int = 3, 74 // hash vpn width 75 hashVpnWidth: Int = 6, 76 // filter 77 ifilterSize: Int = 8, 78 dfilterSize: Int = 32, 79 // miss queue, add more entries than 'must require' 80 // 0 for easier bug trigger, please set as big as u can, 8 maybe 81 missqueueExtendSize: Int = 0, 82 // llptw 83 llptwsize: Int = 6, 84 // way size 85 blockBytes: Int = 64, 86 // prefetch 87 enablePrefetch: Boolean = true, 88 // ecc 89 ecc: Option[String] = Some("secded"), 90 // enable ecc 91 enablePTWECC: Boolean = false 92) 93 94trait HasTlbConst extends HasXSParameter { 95 val Level = if (EnableSv48) 3 else 2 96 97 val offLen = 12 98 val ppnLen = PAddrBits - offLen 99 val vpnnLen = 9 100 val extendVpnnBits = if (HasHExtension) 2 else 0 101 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 102 /* 103 Sv39 page table entry 104 +--+------+--------+----------------------+-----+--------+ 105 |63|62 61|60 54|53 10|9 8|7 0| 106 +--+------+--------+----------------------+-----+--------+ 107 |N | PBMT |Reserved| PPNs | RSW | FALG | 108 +--+------+--------+----------------------+-----+--------+ 109 */ 110 val pteFlagLen = 8 111 val pteRswLen = 2 112 val ptePPNLen = 44 113 val ptePaddrLen = 56 114 val pteResLen = 7 115 val ptePbmtLen = 2 116 val pteNLen = 1 117 val pteNapotBits = 4 118 val ppnHignLen = ptePPNLen - ppnLen 119 val gvpnLen = GPAddrBits - offLen 120 121 val tlbcontiguous = 8 122 val sectortlbwidth = log2Up(tlbcontiguous) 123 val sectorppnLen = ppnLen - sectortlbwidth 124 val sectorgvpnLen = gvpnLen - sectortlbwidth 125 val sectorvpnLen = vpnLen - sectortlbwidth 126 val sectorptePPNLen = ptePPNLen - sectortlbwidth 127 128 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 129 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 130 val prefetchfiltersize = 8 131 132 val sramSinglePort = true 133 134 val timeOutThreshold = 100000 135 136 def noS2xlate = "b00".U 137 def allStage = "b11".U 138 def onlyStage1 = "b01".U 139 def onlyStage2 = "b10".U 140 141 def Sv39 = "h8".U 142 def Sv48 = "h9".U 143 144 def Sv39x4 = "h8".U 145 def Sv48x4 = "h9".U 146 147 def PMLEN7 = "b10".U 148 def PMLEN16 = "b11".U 149 def MaxMaskedWidth = 16 150 151 def get_pn(addr: UInt) = { 152 require(addr.getWidth > offLen) 153 addr(addr.getWidth-1, offLen) 154 } 155 def get_off(addr: UInt) = { 156 require(addr.getWidth > offLen) 157 addr(offLen-1, 0) 158 } 159 160 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 161 require(nSets >= 1) 162 vpn(log2Up(nSets)-1, 0) 163 } 164 165 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 166 require(nSets >= 1) 167 require(vpn.getWidth > log2Ceil(nSets)) 168 vpn(vpn.getWidth-1, log2Ceil(nSets)) 169 } 170 171 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 172 require(nSets >= 1) 173 require(vpn1.getWidth == vpn2.getWidth) 174 if (vpn1.getWidth <= log2Ceil(nSets)) { 175 true.B 176 } else { 177 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 178 } 179 } 180 181 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 182 val width = v.getWidth 183 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 184 val full = Cat(v).andR 185 Mux(full, lruIdx, emptyIdx) 186 } 187 188 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 189 replaceWrapper(VecInit(v).asUInt, lruIdx) 190 } 191 192 import scala.language.implicitConversions 193 194 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 195 val tp = Wire(new TlbPermBundle) 196 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 197 tp.pf := hptwResp.gpf 198 tp.af := hptwResp.gaf 199 tp.v := DontCare 200 tp.d := ptePerm.d 201 tp.a := ptePerm.a 202 tp.g := ptePerm.g 203 tp.u := ptePerm.u 204 tp.x := ptePerm.x 205 tp.w := ptePerm.w 206 tp.r := ptePerm.r 207 tp 208 } 209 210 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 211 val tp = Wire(new TlbPermBundle) 212 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 213 tp.pf := ptwResp.pf 214 tp.af := ptwResp.af 215 tp.v := ptwResp.entry.v 216 tp.d := ptePerm.d 217 tp.a := ptePerm.a 218 tp.g := ptePerm.g 219 tp.u := ptePerm.u 220 tp.x := ptePerm.x 221 tp.w := ptePerm.w 222 tp.r := ptePerm.r 223 tp 224 } 225} 226 227trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 228 val PtwWidth = 2 229 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 230 val prefetchID = PtwWidth 231 232 val blockBits = l2tlbParams.blockBytes * 8 233 234 val bPtwWidth = log2Up(PtwWidth) 235 val bSourceWidth = log2Up(sourceWidth) 236 // ptwl3: fully-associated 237 val PtwL3TagLen = if (EnableSv48) vpnnLen + extendVpnnBits else 0 238 // ptwl2: fully-associated 239 val PtwL2TagLen = if (EnableSv48) vpnnLen * 2 + extendVpnnBits else vpnnLen + extendVpnnBits 240 241 /* +-------+----------+-------------+ 242 * | Tag | SetIdx | SectorIdx | 243 * +-------+----------+-------------+ 244 */ 245 // ptwl1: 8-way group-associated 246 val PtwL1SetNum = l2tlbParams.l1nSets 247 val PtwL1SectorSize = blockBits / XLEN 248 val PtwL1IdxLen = log2Up(PtwL1SetNum * PtwL1SectorSize) 249 val PtwL1SectorIdxLen = log2Up(PtwL1SectorSize) 250 val PtwL1SetIdxLen = log2Up(PtwL1SetNum) 251 val PtwL1TagLen = if (EnableSv48) vpnnLen * 3 - PtwL1IdxLen + extendVpnnBits else vpnnLen * 2 - PtwL1IdxLen + extendVpnnBits 252 253 // ptwl0: 16-way group-associated 254 val PtwL0SetNum = l2tlbParams.l0nSets 255 val PtwL0SectorSize = blockBits / XLEN 256 val PtwL0IdxLen = log2Up(PtwL0SetNum * PtwL0SectorSize) 257 val PtwL0SectorIdxLen = log2Up(PtwL0SectorSize) 258 val PtwL0SetIdxLen = log2Up(PtwL0SetNum) 259 val PtwL0TagLen = if (EnableSv48) vpnnLen * 4 - PtwL0IdxLen + extendVpnnBits else vpnnLen * 3 - PtwL0IdxLen + extendVpnnBits 260 261 // super page, including 512GB, 1GB, 2MB page && Svnapot page 262 val SPTagLen = if (EnableSv48) vpnnLen * 4 + extendVpnnBits else vpnnLen * 3 + extendVpnnBits 263 264 // miss queue 265 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 266 val MemReqWidth = if (HasBitmapCheck) 2 *(l2tlbParams.llptwsize + 1 + 1) else (l2tlbParams.llptwsize + 1 + 1) 267 val HptwReqId = l2tlbParams.llptwsize + 1 268 val FsmReqID = l2tlbParams.llptwsize 269 val bMemID = log2Up(MemReqWidth) 270 271 def ptwTranVec(flushMask: UInt): Vec[Bool] = { 272 val vec = Wire(Vec(tlbcontiguous, Bool())) 273 for (i <- 0 until tlbcontiguous) { 274 vec(i) := flushMask(i) 275 } 276 vec 277 } 278 279 def dupBitmapPPN(ppn1: UInt, ppn2: UInt) : Bool = { 280 ppn1(ppnLen-1, ppnLen-log2Up(XLEN)) === ppn2(ppnLen-1, ppnLen-log2Up(XLEN)) 281 } 282 283 def genPtwL1Idx(vpn: UInt) = { 284 (vpn(vpnLen - 1, vpnnLen))(PtwL1IdxLen - 1, 0) 285 } 286 287 def genPtwL1SectorIdx(vpn: UInt) = { 288 genPtwL1Idx(vpn)(PtwL1SectorIdxLen - 1, 0) 289 } 290 291 def genPtwL1SetIdx(vpn: UInt) = { 292 genPtwL1Idx(vpn)(PtwL1SetIdxLen + PtwL1SectorIdxLen - 1, PtwL1SectorIdxLen) 293 } 294 295 def genPtwL0Idx(vpn: UInt) = { 296 vpn(PtwL0IdxLen - 1, 0) 297 } 298 299 def genPtwL0SectorIdx(vpn: UInt) = { 300 genPtwL0Idx(vpn)(PtwL0SectorIdxLen - 1, 0) 301 } 302 303 def dropL0SectorBits(vpn: UInt) = { 304 vpn(vpn.getWidth-1, PtwL0SectorIdxLen) 305 } 306 307 def genPtwL0SetIdx(vpn: UInt) = { 308 genPtwL0Idx(vpn)(PtwL0SetIdxLen + PtwL0SectorIdxLen - 1, PtwL0SectorIdxLen) 309 } 310 311 def MakeAddr(ppn: UInt, off: UInt) = { 312 require(off.getWidth == 9) 313 Cat(ppn, off, 0.U(log2Up(XLEN/8).W)) 314 } 315 316 def MakeGPAddr(ppn: UInt, off: UInt) = { 317 require(off.getWidth == 9 || off.getWidth == 11) 318 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 319 } 320 321 def getVpnn(vpn: UInt, idx: Int): UInt = { 322 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 323 } 324 325 def getVpnn(vpn: UInt, idx: UInt): UInt = { 326 MuxLookup(idx, 0.U)(Seq( 327 0.U -> vpn(vpnnLen - 1, 0), 328 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 329 2.U -> vpn(vpnnLen * 3 - 1, vpnnLen * 2), 330 3.U -> vpn(vpnnLen * 4 - 1, vpnnLen * 3)) 331 ) 332 } 333 334 def getGVpnn(vpn: UInt, idx: UInt, mode: UInt): UInt = { 335 MuxLookup(idx, 0.U)(Seq( 336 0.U -> vpn(vpnnLen - 1, 0), 337 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 338 2.U -> Mux(mode === Sv48, vpn(vpnnLen * 3 - 1, vpnnLen * 2), vpn(vpnnLen * 3 + 1, vpnnLen * 2)), 339 3.U -> vpn(vpnnLen * 4 + 1, vpnnLen * 3)) 340 ) 341 } 342 343 def getVpnClip(vpn: UInt, level: Int) = { 344 // level 2 /* vpnn2 */ 345 // level 1 /* vpnn2 * vpnn1 */ 346 // level 0 /* vpnn2 * vpnn1 * vpnn0*/ 347 vpn(vpnLen - 1, level * vpnnLen) 348 } 349 350 def get_next_line(vpn: UInt) = { 351 Cat(dropL0SectorBits(vpn) + 1.U, 0.U(PtwL0SectorIdxLen.W)) 352 } 353 354 def same_l1entry(vpn1: UInt, vpn2: UInt) = { 355 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 356 } 357 358 def from_pre(source: UInt) = { 359 (source === prefetchID.U) 360 } 361 362 def sel_data(data: UInt, index: UInt): UInt = { 363 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 364 inner_data(index) 365 } 366 367 // vpn1 and vpn2 is at same cacheline 368 def dup(vpn1: UInt, vpn2: UInt): Bool = { 369 dropL0SectorBits(vpn1) === dropL0SectorBits(vpn2) 370 } 371 372 373 def printVec[T <: Data](x: Seq[T]): Printable = { 374 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 375 } 376} 377