1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 22import utils._ 23import xiangshan._ 24import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle} 25import xiangshan.cache.mmu._ 26import xiangshan.frontend.icache._ 27 28 29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 30 31 val instrUncache = LazyModule(new InstrUncache()) 32 val icache = LazyModule(new ICache()) 33 34 lazy val module = new FrontendImp(this) 35} 36 37 38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 39 with HasXSParameter 40 with HasPerfEvents 41{ 42 val io = IO(new Bundle() { 43 val hartId = Input(UInt(8.W)) 44 val reset_vector = Input(UInt(PAddrBits.W)) 45 val fencei = Input(Bool()) 46 val ptw = new VectorTlbPtwIO(4) 47 val backend = new FrontendToCtrlIO 48 val sfence = Input(new SfenceBundle) 49 val tlbCsr = Input(new TlbCsrBundle) 50 val csrCtrl = Input(new CustomCSRCtrlIO) 51 val csrUpdate = new DistributedCSRUpdateReq 52 val error = new L1CacheErrorInfo 53 val frontendInfo = new Bundle { 54 val ibufFull = Output(Bool()) 55 val bpuInfo = new Bundle { 56 val bpRight = Output(UInt(XLEN.W)) 57 val bpWrong = Output(UInt(XLEN.W)) 58 } 59 } 60 }) 61 62 //decouped-frontend modules 63 val instrUncache = outer.instrUncache.module 64 val icache = outer.icache.module 65 val bpu = Module(new Predictor) 66 val ifu = Module(new NewIFU) 67 val ibuffer = Module(new Ibuffer) 68 val ftq = Module(new Ftq) 69 70 val needFlush = RegNext(io.backend.toFtq.redirect.valid) 71 72 val tlbCsr = DelayN(io.tlbCsr, 2) 73 val csrCtrl = DelayN(io.csrCtrl, 2) 74 val sfence = RegNext(RegNext(io.sfence)) 75 76 // trigger 77 ifu.io.frontendTrigger := csrCtrl.frontend_trigger 78 val triggerEn = csrCtrl.trigger_enable 79 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 80 81 // bpu ctrl 82 bpu.io.ctrl := csrCtrl.bp_ctrl 83 bpu.io.reset_vector := io.reset_vector 84 85// pmp 86 val pmp = Module(new PMP()) 87 val pmp_check = VecInit(Seq.fill(4)(Module(new PMPChecker(3, sameCycle = true)).io)) 88 pmp.io.distribute_csr := csrCtrl.distribute_csr 89 val pmp_req_vec = Wire(Vec(4, Valid(new PMPReqBundle()))) 90 pmp_req_vec(0) <> icache.io.pmp(0).req 91 pmp_req_vec(1) <> icache.io.pmp(1).req 92 pmp_req_vec(2) <> icache.io.pmp(2).req 93 pmp_req_vec(3) <> ifu.io.pmp.req 94 95 for (i <- pmp_check.indices) { 96 pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i)) 97 } 98 icache.io.pmp(0).resp <> pmp_check(0).resp 99 icache.io.pmp(1).resp <> pmp_check(1).resp 100 icache.io.pmp(2).resp <> pmp_check(2).resp 101 ifu.io.pmp.resp <> pmp_check(3).resp 102 103 val itlb = Module(new TLB(4, nRespDups = 1, Seq(true, true, false, true), itlbParams)) 104 itlb.io.requestor.take(3) zip icache.io.itlb foreach {case (a,b) => a <> b} 105 itlb.io.requestor(3) <> ifu.io.iTLBInter // mmio may need re-tlb, blocked 106 itlb.io.base_connect(io.sfence, tlbCsr) 107 io.ptw.connect(itlb.io.ptw) 108 itlb.io.ptw_replenish <> DontCare 109 itlb.io.flushPipe.map(_ := needFlush) 110 111 icache.io.prefetch <> ftq.io.toPrefetch 112 113 114 //IFU-Ftq 115 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 116 ftq.io.toIfu.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 117 118 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 119 bpu.io.ftq_to_bpu <> ftq.io.toBpu 120 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 121 //IFU-ICache 122 123 icache.io.fetch.req <> ftq.io.toICache.req 124 ftq.io.toICache.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 125 126 ifu.io.icacheInter.resp <> icache.io.fetch.resp 127 ifu.io.icacheInter.req.ready := DontCare 128 icache.io.stop := ifu.io.icacheStop 129 130 ifu.io.icachePerfInfo := icache.io.perfInfo 131 132 icache.io.csr.distribute_csr <> csrCtrl.distribute_csr 133 io.csrUpdate := RegNext(icache.io.csr.update) 134 135 icache.io.csr_pf_enable := RegNext(csrCtrl.l1I_pf_enable) 136 icache.io.csr_parity_enable := RegNext(csrCtrl.icache_parity_enable) 137 138 //IFU-Ibuffer 139 ifu.io.toIbuffer <> ibuffer.io.in 140 141 ftq.io.fromBackend <> io.backend.toFtq 142 io.backend.fromFtq <> ftq.io.toBackend 143 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 144 145 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 146 147 ibuffer.io.flush := needFlush 148 io.backend.cfVec <> ibuffer.io.out 149 150 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 151 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 152 instrUncache.io.flush := false.B 153 io.error <> RegNext(RegNext(icache.io.error)) 154 155 icache.io.hartId := io.hartId 156 157 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 158 XSPerfAccumulate("FrontendBubble", frontendBubble) 159 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 160 161 // PFEvent 162 val pfevent = Module(new PFEvent) 163 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 164 val csrevents = pfevent.io.hpmevent.take(8) 165 166 val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf) 167 override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents 168 generatePerfEvent() 169} 170