1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import chipsalliance.rocketchip.config.Parameters 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.PipelineConnect 8import xiangshan._ 9import xiangshan.cache._ 10import xiangshan.cache.prefetch.L1plusPrefetcher 11import xiangshan.backend.fu.HasExceptionNO 12 13class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 14 15 val instrUncache = LazyModule(new InstrUncache()) 16 17 lazy val module = new FrontendImp(this) 18} 19 20 21class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 22 with HasL1plusCacheParameters 23 with HasXSParameter 24 with HasExceptionNO 25 with HasXSLog 26{ 27 val io = IO(new Bundle() { 28 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 29 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 30 val l1plusFlush = Output(Bool()) 31 val fencei = Input(Bool()) 32 val ptw = new TlbPtwIO 33 val backend = new FrontendToBackendIO 34 val sfence = Input(new SfenceBundle) 35 val tlbCsr = Input(new TlbCsrBundle) 36 }) 37 38 val ifu = Module(new IFU) 39 val ibuffer = Module(new Ibuffer) 40 val l1plusPrefetcher = Module(new L1plusPrefetcher) 41 val instrUncache = outer.instrUncache.module 42 43 val needFlush = io.backend.redirect_cfiUpdate.valid 44 45 // from backend 46 ifu.io.redirect <> io.backend.redirect_cfiUpdate 47 ifu.io.commitUpdate <> io.backend.commit_cfiUpdate 48 ifu.io.ftqEnqPtr <> io.backend.ftqEnqPtr 49 ifu.io.ftqLeftOne <> io.backend.ftqLeftOne 50 // to icache 51 val grantClientId = clientId(io.icacheMemGrant.bits.id) 52 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 53 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 54 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 55 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 56 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 57 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 58 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 59 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 60 ifu.io.icacheMemGrant.ready, 61 l1plusPrefetcher.io.mem_grant.ready) 62 ifu.io.fencei := io.fencei 63 64 65 instrUncache.io.req <> ifu.io.mmio_acquire 66 instrUncache.io.resp <> ifu.io.mmio_grant 67 instrUncache.io.flush <> ifu.io.mmio_flush 68 // to tlb 69 ifu.io.sfence := io.sfence 70 ifu.io.tlbCsr := io.tlbCsr 71 // from icache and l1plus prefetcher 72 io.l1plusFlush := ifu.io.l1plusFlush 73 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 74 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 75 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 76 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 77 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 78 entryId(ifu.io.icacheMemAcq.bits.id)) 79 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 80 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 81 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 82 io.icacheMemAcq <> memAcquireArb.io.out 83 // itlb to ptw 84 io.ptw <> ifu.io.ptw 85 // ifu to ibuffer 86 ibuffer.io.in <> ifu.io.fetchPacket 87 // backend to ibuffer 88 ibuffer.io.flush := needFlush 89 // ibuffer to backend 90 io.backend.cfVec <> ibuffer.io.out 91 // ifu to backend 92 io.backend.fetchInfo <> ifu.io.toFtq 93 94 // for(out <- ibuffer.io.out){ 95 // XSInfo(out.fire(), 96 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 97 // ) 98 // } 99 100 101}