1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import utils._ 19import chisel3._ 20import chisel3.util._ 21import chipsalliance.rocketchip.config.Parameters 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.mmu.{TlbRequestIO, TlbPtwIO,TLB} 26import xiangshan.backend.fu.{HasExceptionNO, PMP, PMPChecker, PFEvent} 27 28 29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 30 31 val instrUncache = LazyModule(new InstrUncache()) 32 val icache = LazyModule(new ICache()) 33 34 lazy val module = new FrontendImp(this) 35} 36 37 38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 39 with HasXSParameter 40 with HasExceptionNO 41{ 42 val io = IO(new Bundle() { 43 val fencei = Input(Bool()) 44 val ptw = new TlbPtwIO(2) 45 val backend = new FrontendToCtrlIO 46 val sfence = Input(new SfenceBundle) 47 val tlbCsr = Input(new TlbCsrBundle) 48 val csrCtrl = Input(new CustomCSRCtrlIO) 49 val csrUpdate = new DistributedCSRUpdateReq 50 val error = new L1CacheErrorInfo 51 val frontendInfo = new Bundle { 52 val ibufFull = Output(Bool()) 53 val bpuInfo = new Bundle { 54 val bpRight = Output(UInt(XLEN.W)) 55 val bpWrong = Output(UInt(XLEN.W)) 56 } 57 } 58 }) 59 60 //decouped-frontend modules 61 val bpu = Module(new Predictor) 62 val ifu = Module(new NewIFU) 63 val ibuffer = Module(new Ibuffer) 64 val ftq = Module(new Ftq) 65 //icache 66 67 //PFEvent 68 val pfevent = Module(new PFEvent) 69 val tlbCsr = RegNext(io.tlbCsr) 70 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 71 72 // trigger 73 ifu.io.frontendTrigger := io.csrCtrl.frontend_trigger 74 val triggerEn = io.csrCtrl.trigger_enable 75 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 76 77 // pmp 78 val pmp = Module(new PMP()) 79 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(3, sameCycle = true)).io)) 80 pmp.io.distribute_csr := io.csrCtrl.distribute_csr 81 for (i <- pmp_check.indices) { 82 pmp_check(i).env.pmp := pmp.io.pmp 83 pmp_check(i).env.pma := pmp.io.pma 84 pmp_check(i).env.mode := tlbCsr.priv.imode 85 pmp_check(i).req <> ifu.io.pmp(i).req 86 ifu.io.pmp(i).resp <> pmp_check(i).resp 87 } 88 89 io.ptw <> TLB( 90 in = Seq(ifu.io.iTLBInter(0), ifu.io.iTLBInter(1)), 91 sfence = io.sfence, 92 csr = tlbCsr, 93 width = 2, 94 shouldBlock = true, 95 itlbParams 96 ) 97 //TODO: modules need to be removed 98 val instrUncache = outer.instrUncache.module 99 val icache = outer.icache.module 100 101 icache.io.fencei := RegNext(io.fencei) 102 103 val needFlush = io.backend.toFtq.stage3Redirect.valid 104 105 //IFU-Ftq 106 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 107 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 108 bpu.io.ftq_to_bpu <> ftq.io.toBpu 109 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 110 //IFU-ICache 111 ifu.io.icacheInter.toIMeta <> icache.io.metaRead.req 112 ifu.io.icacheInter.fromIMeta <> icache.io.metaRead.resp 113 ifu.io.icacheInter.toIData <> icache.io.dataRead.req 114 ifu.io.icacheInter.fromIData <> icache.io.dataRead.resp 115 116 for(i <- 0 until 2){ 117 ifu.io.icacheInter.toMissQueue(i) <> icache.io.missQueue.req(i) 118 ifu.io.icacheInter.fromMissQueue(i) <> icache.io.missQueue.resp(i) 119 } 120 121 icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid) 122 123 icache.io.csr.distribute_csr <> io.csrCtrl.distribute_csr 124 icache.io.csr.update <> io.csrUpdate 125 126 //IFU-Ibuffer 127 ifu.io.toIbuffer <> ibuffer.io.in 128 129 ftq.io.fromBackend <> io.backend.toFtq 130 io.backend.fromFtq <> ftq.io.toBackend 131 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 132 133 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 134 135 ibuffer.io.flush := needFlush 136 io.backend.cfVec <> ibuffer.io.out 137 138 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 139 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 140 instrUncache.io.flush := icache.io.missQueue.flush 141 io.error <> DontCare 142 143 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 144 XSPerfAccumulate("FrontendBubble", frontendBubble) 145 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 146 147 if(print_perfcounter){ 148 val ifu_perf = ifu.perfEvents.map(_._1).zip(ifu.perfinfo.perfEvents.perf_events) 149 val ibuffer_perf = ibuffer.perfEvents.map(_._1).zip(ibuffer.perfinfo.perfEvents.perf_events) 150 val icache_perf = icache.perfEvents.map(_._1).zip(icache.perfinfo.perfEvents.perf_events) 151 val ftq_perf = ftq.perfEvents.map(_._1).zip(ftq.perfinfo.perfEvents.perf_events) 152 val bpu_perf = bpu.perfEvents.map(_._1).zip(bpu.perfinfo.perfEvents.perf_events) 153 val perfEvents = ifu_perf ++ ibuffer_perf ++ icache_perf ++ ftq_perf ++ bpu_perf 154 155 for (((perf_name,perf),i) <- perfEvents.zipWithIndex) { 156 println(s"frontend perf $i: $perf_name") 157 } 158 } 159 160 val hpmEvents = ifu.perfinfo.perfEvents.perf_events ++ ibuffer.perfinfo.perfEvents.perf_events ++ 161 icache.perfinfo.perfEvents.perf_events ++ ftq.perfinfo.perfEvents.perf_events ++ 162 bpu.perfinfo.perfEvents.perf_events 163 val perf_length = hpmEvents.length 164 val csrevents = pfevent.io.hpmevent.slice(0,8) 165 val perfinfo = IO(new Bundle(){ 166 val perfEvents = Output(new PerfEventsBundle(csrevents.length)) 167 }) 168 val hpm_frontend = Module(new HPerfmonitor(perf_length,csrevents.length)) 169 hpm_frontend.io.hpm_event := csrevents 170 hpm_frontend.io.events_sets.perf_events := hpmEvents 171 perfinfo.perfEvents := RegNext(hpm_frontend.io.events_selected) 172} 173