1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import utils._ 19import chisel3._ 20import chisel3.util._ 21import chipsalliance.rocketchip.config.Parameters 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.mmu.{TlbRequestIO, TlbPtwIO,TLB} 26import xiangshan.backend.fu.HasExceptionNO 27import system.L1CacheErrorInfo 28 29 30class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 31 32 val instrUncache = LazyModule(new InstrUncache()) 33 val icache = LazyModule(new ICache()) 34 35 lazy val module = new FrontendImp(this) 36} 37 38 39class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 40 with HasXSParameter 41 with HasExceptionNO 42{ 43 val io = IO(new Bundle() { 44 val fencei = Input(Bool()) 45 val ptw = new TlbPtwIO(2) 46 val backend = new FrontendToCtrlIO 47 val sfence = Input(new SfenceBundle) 48 val tlbCsr = Input(new TlbCsrBundle) 49 val csrCtrl = Input(new CustomCSRCtrlIO) 50 val error = new L1CacheErrorInfo 51 val frontendInfo = new Bundle { 52 val ibufFull = Output(Bool()) 53 val bpuInfo = new Bundle { 54 val bpRight = Output(UInt(XLEN.W)) 55 val bpWrong = Output(UInt(XLEN.W)) 56 } 57 } 58 }) 59 60 //decouped-frontend modules 61 val bpu = Module(new Predictor) 62 val ifu = Module(new NewIFU) 63 val ibuffer = Module(new Ibuffer) 64 val ftq = Module(new Ftq) 65 //icache 66 67 io.ptw <> TLB( 68 in = Seq(ifu.io.iTLBInter(0), ifu.io.iTLBInter(1)), 69 sfence = io.sfence, 70 csr = io.tlbCsr, 71 width = 2, 72 shouldBlock = true, 73 itlbParams 74 ) 75 //TODO: modules need to be removed 76 val instrUncache = outer.instrUncache.module 77 val icache = outer.icache.module 78 79 icache.io.fencei := RegNext(io.fencei) 80 81 val needFlush = io.backend.toFtq.stage3Redirect.valid 82 83 //IFU-Ftq 84 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 85 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 86 bpu.io.ftq_to_bpu <> ftq.io.toBpu 87 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 88 //IFU-ICache 89 ifu.io.icacheInter.toIMeta <> icache.io.metaRead.req 90 ifu.io.icacheInter.fromIMeta <> icache.io.metaRead.resp 91 ifu.io.icacheInter.toIData <> icache.io.dataRead.req 92 ifu.io.icacheInter.fromIData <> icache.io.dataRead.resp 93 94 for(i <- 0 until 2){ 95 ifu.io.icacheInter.toMissQueue(i) <> icache.io.missQueue.req(i) 96 ifu.io.icacheInter.fromMissQueue(i) <> icache.io.missQueue.resp(i) 97 } 98 99 icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid) 100 101 //IFU-Ibuffer 102 ifu.io.toIbuffer <> ibuffer.io.in 103 104 ftq.io.fromBackend <> io.backend.toFtq 105 io.backend.fromFtq <> ftq.io.toBackend 106 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 107 108 ibuffer.io.flush := needFlush 109 io.backend.cfVec <> ibuffer.io.out 110 111 instrUncache.io.req <> DontCare 112 instrUncache.io.resp <> DontCare 113 instrUncache.io.flush <> DontCare 114 io.error <> DontCare 115 116 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 117 XSPerfAccumulate("FrontendBubble", frontendBubble) 118 119 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 120} 121