1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 22import utils._ 23import xiangshan._ 24import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle} 25import xiangshan.cache.mmu._ 26import xiangshan.frontend.icache._ 27 28 29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 30 31 val instrUncache = LazyModule(new InstrUncache()) 32 val icache = LazyModule(new ICache()) 33 34 lazy val module = new FrontendImp(this) 35} 36 37 38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 39 with HasXSParameter 40 with HasPerfEvents 41{ 42 val io = IO(new Bundle() { 43 val fencei = Input(Bool()) 44 val ptw = new TlbPtwIO(6) 45 val backend = new FrontendToCtrlIO 46 val sfence = Input(new SfenceBundle) 47 val tlbCsr = Input(new TlbCsrBundle) 48 val csrCtrl = Input(new CustomCSRCtrlIO) 49 val csrUpdate = new DistributedCSRUpdateReq 50 val error = new L1CacheErrorInfo 51 val frontendInfo = new Bundle { 52 val ibufFull = Output(Bool()) 53 val bpuInfo = new Bundle { 54 val bpRight = Output(UInt(XLEN.W)) 55 val bpWrong = Output(UInt(XLEN.W)) 56 } 57 } 58 }) 59 60 //decouped-frontend modules 61 val instrUncache = outer.instrUncache.module 62 val icache = outer.icache.module 63 val bpu = Module(new Predictor) 64 val ifu = Module(new NewIFU) 65 val ibuffer = Module(new Ibuffer) 66 val ftq = Module(new Ftq) 67 68 val tlbCsr = DelayN(io.tlbCsr, 2) 69 val csrCtrl = DelayN(io.csrCtrl, 2) 70 71 // trigger 72 ifu.io.frontendTrigger := csrCtrl.frontend_trigger 73 val triggerEn = csrCtrl.trigger_enable 74 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 75 76// pmp 77 val pmp = Module(new PMP()) 78 val pmp_check = VecInit(Seq.fill(4)(Module(new PMPChecker(3, sameCycle = true)).io)) 79 pmp.io.distribute_csr := csrCtrl.distribute_csr 80 val pmp_req_vec = Wire(Vec(4, Valid(new PMPReqBundle()))) 81 pmp_req_vec(0) <> icache.io.pmp(0).req 82 pmp_req_vec(1) <> icache.io.pmp(1).req 83 pmp_req_vec(2) <> icache.io.pmp(2).req 84 pmp_req_vec(3) <> ifu.io.pmp.req 85 86 for (i <- pmp_check.indices) { 87 pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i)) 88 } 89 icache.io.pmp(0).resp <> pmp_check(0).resp 90 icache.io.pmp(1).resp <> pmp_check(1).resp 91 icache.io.pmp(2).resp <> pmp_check(2).resp 92 ifu.io.pmp.resp <> pmp_check(3).resp 93 94 // val tlb_req_arb = Module(new Arbiter(new TlbReq, 2)) 95 // tlb_req_arb.io.in(0) <> ifu.io.iTLBInter.req 96 // tlb_req_arb.io.in(1) <> icache.io.itlb(1).req 97 98 val itlb_requestors = Wire(Vec(6, new BlockTlbRequestIO)) 99 itlb_requestors(0) <> icache.io.itlb(0) 100 itlb_requestors(1) <> icache.io.itlb(1) 101 itlb_requestors(2) <> icache.io.itlb(2) 102 itlb_requestors(3) <> icache.io.itlb(3) 103 itlb_requestors(4) <> icache.io.itlb(4) 104 itlb_requestors(5) <> ifu.io.iTLBInter 105 106 // itlb_requestors(1).req <> tlb_req_arb.io.out 107 108 // ifu.io.iTLBInter.resp <> itlb_requestors(1).resp 109 // icache.io.itlb(1).resp <> itlb_requestors(1).resp 110 111 io.ptw <> TLB( 112 //in = Seq(icache.io.itlb(0), icache.io.itlb(1)), 113 in = Seq(itlb_requestors(0),itlb_requestors(1),itlb_requestors(2),itlb_requestors(3),itlb_requestors(4),itlb_requestors(5)), 114 sfence = io.sfence, 115 csr = tlbCsr, 116 width = 6, 117 shouldBlock = true, 118 itlbParams 119 ) 120 121 icache.io.prefetch <> ftq.io.toPrefetch 122 123 val needFlush = RegNext(io.backend.toFtq.redirect.valid) 124 125 //IFU-Ftq 126 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 127 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 128 bpu.io.ftq_to_bpu <> ftq.io.toBpu 129 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 130 //IFU-ICache 131 for(i <- 0 until 2){ 132 ifu.io.icacheInter(i).req <> icache.io.fetch(i).req 133 icache.io.fetch(i).req <> ifu.io.icacheInter(i).req 134 ifu.io.icacheInter(i).resp <> icache.io.fetch(i).resp 135 } 136 icache.io.stop := ifu.io.icacheStop 137 138 ifu.io.icachePerfInfo := icache.io.perfInfo 139 140 icache.io.csr.distribute_csr <> csrCtrl.distribute_csr 141 io.csrUpdate := RegNext(icache.io.csr.update) 142 143 icache.io.csr_pf_enable := RegNext(csrCtrl.l1I_pf_enable) 144 icache.io.csr_parity_enable := RegNext(csrCtrl.icache_parity_enable) 145 146 //IFU-Ibuffer 147 ifu.io.toIbuffer <> ibuffer.io.in 148 149 ftq.io.fromBackend <> io.backend.toFtq 150 io.backend.fromFtq <> ftq.io.toBackend 151 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 152 153 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 154 155 ibuffer.io.flush := needFlush 156 io.backend.cfVec <> ibuffer.io.out 157 158 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 159 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 160 instrUncache.io.flush := false.B 161 io.error <> RegNext(RegNext(icache.io.error)) 162 163 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 164 XSPerfAccumulate("FrontendBubble", frontendBubble) 165 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 166 167 // PFEvent 168 val pfevent = Module(new PFEvent) 169 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 170 val csrevents = pfevent.io.hpmevent.take(8) 171 172 val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf) 173 override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents 174 generatePerfEvent() 175} 176