1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8 9 10class Frontend extends XSModule { 11 val io = IO(new Bundle() { 12 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 13 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 14 val l1plusFlush = Output(Bool()) 15 val fencei = Input(Bool()) 16 val ptw = new TlbPtwIO 17 val backend = new FrontendToBackendIO 18 val sfence = Input(new SfenceBundle) 19 val tlbCsr = Input(new TlbCsrBundle) 20 }) 21 22 val ifu = Module(new IFU) 23 val ibuffer = Module(new Ibuffer) 24 val icache = Module(new ICache) 25 26 val needFlush = io.backend.redirect.valid 27 28 //backend 29 ifu.io.redirect <> io.backend.redirect 30 ifu.io.inOrderBrInfo <> io.backend.inOrderBrInfo 31 ifu.io.outOfOrderBrInfo <> io.backend.outOfOrderBrInfo 32 //icache 33 ifu.io.icacheResp <> icache.io.resp 34 icache.io.req <> ifu.io.icacheReq 35 icache.io.flush <> ifu.io.icacheFlush 36 icache.io.fencei := io.fencei 37 io.l1plusFlush := icache.io.l1plusflush 38 io.icacheMemAcq <> icache.io.mem_acquire 39 icache.io.mem_grant <> io.icacheMemGrant 40 //itlb to ptw 41 io.ptw <> TLB( 42 in = Seq(icache.io.tlb), 43 sfence = io.sfence, 44 csr = io.tlbCsr, 45 width = 1, 46 isDtlb = false, 47 shouldBlock = true 48 ) 49 //ibuffer 50 ibuffer.io.in <> ifu.io.fetchPacket 51 ibuffer.io.flush := needFlush 52 53 io.backend.cfVec <> ibuffer.io.out 54 55 // for(out <- ibuffer.io.out){ 56 // XSInfo(out.fire(), 57 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 58 // ) 59 // } 60 61 62}