1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 22import utils._ 23import xiangshan._ 24import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker} 25import xiangshan.cache.mmu.{TLB, TlbPtwIO} 26import xiangshan.frontend.icache._ 27 28 29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 30 31 val instrUncache = LazyModule(new InstrUncache()) 32 val icache = LazyModule(new ICache()) 33 34 lazy val module = new FrontendImp(this) 35} 36 37 38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 39 with HasXSParameter 40 with HasPerfEvents 41{ 42 val io = IO(new Bundle() { 43 val fencei = Input(Bool()) 44 val ptw = new TlbPtwIO(2) 45 val backend = new FrontendToCtrlIO 46 val sfence = Input(new SfenceBundle) 47 val tlbCsr = Input(new TlbCsrBundle) 48 val csrCtrl = Input(new CustomCSRCtrlIO) 49 val csrUpdate = new DistributedCSRUpdateReq 50 val error = new L1CacheErrorInfo 51 val frontendInfo = new Bundle { 52 val ibufFull = Output(Bool()) 53 val bpuInfo = new Bundle { 54 val bpRight = Output(UInt(XLEN.W)) 55 val bpWrong = Output(UInt(XLEN.W)) 56 } 57 } 58 }) 59 60 //decouped-frontend modules 61 val instrUncache = outer.instrUncache.module 62 val icache = outer.icache.module 63 val bpu = Module(new Predictor) 64 val ifu = Module(new NewIFU) 65 val ibuffer = Module(new Ibuffer) 66 val ftq = Module(new Ftq) 67 68 val tlbCsr = DelayN(io.tlbCsr, 2) 69 val csrCtrl = DelayN(io.csrCtrl, 2) 70 71 // trigger 72 ifu.io.frontendTrigger := csrCtrl.frontend_trigger 73 val triggerEn = csrCtrl.trigger_enable 74 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 75 76 // pmp 77 val pmp = Module(new PMP()) 78 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(3, sameCycle = true)).io)) 79 pmp.io.distribute_csr := csrCtrl.distribute_csr 80 for (i <- pmp_check.indices) { 81 pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, icache.io.pmp(i).req) 82 icache.io.pmp(i).resp <> pmp_check(i).resp 83 } 84 85 io.ptw <> TLB( 86 in = Seq(icache.io.itlb(0), icache.io.itlb(1)), 87 sfence = io.sfence, 88 csr = tlbCsr, 89 width = 2, 90 shouldBlock = true, 91 itlbParams 92 ) 93 94 icache.io.fencei := RegNext(io.fencei) 95 96 val needFlush = RegNext(io.backend.toFtq.redirect.valid) 97 98 //IFU-Ftq 99 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 100 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 101 bpu.io.ftq_to_bpu <> ftq.io.toBpu 102 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 103 //IFU-ICache 104 for(i <- 0 until 2){ 105 ifu.io.icacheInter(i).req <> icache.io.fetch(i).req 106 icache.io.fetch(i).req <> ifu.io.icacheInter(i).req 107 ifu.io.icacheInter(i).resp <> icache.io.fetch(i).resp 108 } 109 icache.io.stop := ifu.io.icacheStop 110 111 ifu.io.icachePerfInfo := icache.io.perfInfo 112 113 //icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid) 114 115 icache.io.csr.distribute_csr <> csrCtrl.distribute_csr 116 io.csrUpdate := RegNext(icache.io.csr.update) 117 118 //IFU-Ibuffer 119 ifu.io.toIbuffer <> ibuffer.io.in 120 121 ftq.io.fromBackend <> io.backend.toFtq 122 io.backend.fromFtq <> ftq.io.toBackend 123 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 124 125 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 126 127 ibuffer.io.flush := needFlush 128 io.backend.cfVec <> ibuffer.io.out 129 130 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 131 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 132 instrUncache.io.flush := false.B//icache.io.missQueue.flush 133 io.error <> DontCare 134 135 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 136 XSPerfAccumulate("FrontendBubble", frontendBubble) 137 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 138 139 // PFEvent 140 val pfevent = Module(new PFEvent) 141 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 142 val csrevents = pfevent.io.hpmevent.take(8) 143 144 val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf) 145 override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents 146 generatePerfEvent() 147} 148