1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.ALUOpType 7import utils._ 8import chisel3.experimental.chiselName 9 10@chiselName 11class RAS extends BasePredictor 12{ 13 class RASResp extends Resp 14 { 15 val target =UInt(VAddrBits.W) 16 } 17 18 class RASBranchInfo extends Meta 19 { 20 val rasSp = UInt(log2Up(RasSize).W) 21 val rasTopCtr = UInt(8.W) 22 val rasToqAddr = UInt(VAddrBits.W) 23 } 24 25 class RASIO extends DefaultBasePredictorIO 26 { 27 val is_ret = Input(Bool()) 28 val callIdx = Flipped(ValidIO(UInt(log2Ceil(PredictWidth).W))) 29 val isRVC = Input(Bool()) 30 val isLastHalfRVI = Input(Bool()) 31 val recover = Flipped(ValidIO(new CfiUpdateInfo)) 32 val out = ValidIO(new RASResp) 33 val meta = Output(new RASBranchInfo) 34 } 35 36 class RASEntry() extends XSBundle { 37 val retAddr = UInt(VAddrBits.W) 38 val ctr = UInt(8.W) // layer of nested call functions 39 } 40 41 def rasEntry() = new RASEntry 42 43 object RASEntry { 44 def apply(retAddr: UInt, ctr: UInt): RASEntry = { 45 val e = Wire(rasEntry()) 46 e.retAddr := retAddr 47 e.ctr := ctr 48 e 49 } 50 } 51 52 override val io = IO(new RASIO) 53 override val debug = true 54 55 @chiselName 56 class RASStack(val rasSize: Int) extends XSModule { 57 val io = IO(new Bundle { 58 val push_valid = Input(Bool()) 59 val pop_valid = Input(Bool()) 60 val new_addr = Input(UInt(VAddrBits.W)) 61 val top_addr = Output(UInt(VAddrBits.W)) 62 val is_empty = Output(Bool()) 63 val is_full = Output(Bool()) 64 val copy_valid = Input(Bool()) 65 val copy_in_mem = Input(Vec(rasSize, rasEntry())) 66 val copy_in_sp = Input(UInt(log2Up(rasSize).W)) 67 val copy_in_top = Input(rasEntry()) 68 val copy_out_mem = Output(Vec(rasSize, rasEntry())) 69 val copy_out_sp = Output(UInt(log2Up(rasSize).W)) 70 val copy_out_top = Output(rasEntry()) 71 72 }) 73 val debugIO = IO(new Bundle{ 74 val write_entry = Output(rasEntry()) 75 val alloc_new = Output(Bool()) 76 val sp = Output(UInt(log2Up(rasSize).W)) 77 val topRegister = Output(rasEntry()) 78 }) 79 @chiselName 80 class Stack(val size: Int) extends XSModule { 81 val io = IO(new Bundle { 82 val rIdx = Input(UInt(log2Up(size).W)) 83 val rdata = Output(rasEntry()) 84 val wen = Input(Bool()) 85 val wIdx = Input(UInt(log2Up(size).W)) 86 val wdata = Input(rasEntry()) 87 val copyen = Input(Bool()) 88 val copy_in = Input(Vec(size, rasEntry())) 89 val copy_out = Output(Vec(size, rasEntry())) 90 }) 91 val mem = Reg(Vec(size, rasEntry())) 92 when (io.wen) { 93 mem(io.wIdx) := io.wdata 94 } 95 io.rdata := mem(io.rIdx) 96 (0 until size).foreach { i => io.copy_out(i) := mem(i) } 97 when (io.copyen) { 98 (0 until size).foreach {i => mem(i) := io.copy_in(i) } 99 } 100 } 101 val sp = RegInit(RasSize.U((log2Up(rasSize) + 1).W)) 102 val topRegister = RegInit(0.U.asTypeOf(new RASEntry)) 103 val stack = Module(new Stack(rasSize)).io 104 105 stack.rIdx := sp - 1.U 106 val top_addr = topRegister.retAddr 107 val top_ctr = topRegister.ctr 108 val alloc_new = io.new_addr =/= top_addr 109 // stack.wen := io.push_valid || io.pop_valid && top_ctr =/= 1.U 110 // stack.wIdx := Mux(io.pop_valid && top_ctr =/= 1.U, sp - 1.U, Mux(alloc_new, sp, sp - 1.U)) 111 // val write_addr = Mux(io.pop_valid && top_ctr =/= 1.U, top_addr, io.new_addr) 112 // val write_ctr = Mux(io.pop_valid && top_ctr =/= 1.U, top_ctr - 1.U, Mux(alloc_new, 1.U, top_ctr + 1.U)) 113 114 stack.wen := io.push_valid && !io.is_empty 115 stack.wIdx := sp 116 val write_addr = topRegister.retAddr 117 val write_ctr = topRegister.ctr 118 119 val write_entry = RASEntry(write_addr, write_ctr) 120 stack.wdata := write_entry 121 debugIO.write_entry := write_entry 122 debugIO.alloc_new := alloc_new 123 debugIO.sp := sp 124 debugIO.topRegister := topRegister 125 126 val is_empty = sp === RasSize.U 127 val is_full = sp === (RasSize - 1).U 128 129 when (io.push_valid && alloc_new) { 130 sp := Mux(is_full, sp, Mux(is_empty, 0.U,sp + 1.U)) 131 top_addr := io.new_addr 132 top_ctr := 1.U 133 } .elsewhen(io.push_valid) { 134 top_ctr := top_ctr + 1.U 135 } 136 137 when (io.pop_valid && top_ctr === 1.U) { 138 sp := Mux(is_empty, sp ,Mux(sp === 0.U, RasSize.U,sp - 1.U)) 139 top_addr := stack.rdata.retAddr 140 top_ctr := stack.rdata.ctr 141 } .elsewhen(io.pop_valid) { 142 top_ctr := top_ctr - 1.U 143 } 144 145 io.copy_out_mem := stack.copy_out 146 io.copy_out_sp := sp 147 io.copy_out_top := topRegister 148 stack.copyen := io.copy_valid 149 stack.copy_in := io.copy_in_mem 150 when (io.copy_valid) { 151 sp := io.copy_in_sp 152 topRegister := io.copy_in_top 153 } 154 155 io.top_addr := top_addr 156 io.is_empty := is_empty 157 io.is_full := is_full 158 } 159 160 // val ras_0 = Reg(Vec(RasSize, rasEntry())) //RegInit(0.U)asTypeOf(Vec(RasSize,rasEntry)) cause comb loop 161 // val ras_1 = Reg(Vec(RasSize, rasEntry())) 162 // val sp_0 = RegInit(0.U(log2Up(RasSize).W)) 163 // val sp_1 = RegInit(0.U(log2Up(RasSize).W)) 164 // val choose_bit = RegInit(false.B) //start with 0 165 // val spec_ras = Mux(choose_bit, ras_1, ras_0) 166 // val spec_sp = Mux(choose_bit,sp_1,sp_0) 167 // val commit_ras = Mux(choose_bit, ras_0, ras_1) 168 // val commit_sp = Mux(choose_bit,sp_0,sp_1) 169 170 // val spec_ras = Reg(Vec(RasSize, rasEntry())) 171 // val spec_sp = RegInit(0.U(log2Up(RasSize).W)) 172 // val commit_ras = Reg(Vec(RasSize, rasEntry())) 173 // val commit_sp = RegInit(0.U(log2Up(RasSize).W)) 174 175 val spec = Module(new RASStack(RasSize)) 176 val spec_ras = spec.io 177 178 179 val spec_push = WireInit(false.B) 180 val spec_pop = WireInit(false.B) 181 val spec_new_addr = packetAligned(io.pc.bits) + (io.callIdx.bits << instOffsetBits.U) + Mux( (io.isRVC | io.isLastHalfRVI) && HasCExtension.B, 2.U, 4.U) 182 spec_ras.push_valid := spec_push 183 spec_ras.pop_valid := spec_pop 184 spec_ras.new_addr := spec_new_addr 185 val spec_is_empty = spec_ras.is_empty 186 val spec_is_full = spec_ras.is_full 187 val spec_top_addr = spec_ras.top_addr 188 189 spec_push := !spec_is_full && io.callIdx.valid && io.pc.valid 190 spec_pop := !spec_is_empty && io.is_ret && io.pc.valid 191 192 val commit = Module(new RASStack(RasSize)) 193 val commit_ras = commit.io 194 195 val commit_push = WireInit(false.B) 196 val commit_pop = WireInit(false.B) 197 val commit_new_addr = Mux(io.recover.bits.pd.isRVC && HasCExtension.B, io.recover.bits.pc + 2.U, io.recover.bits.pc + 4.U) 198 commit_ras.push_valid := commit_push 199 commit_ras.pop_valid := commit_pop 200 commit_ras.new_addr := commit_new_addr 201 val commit_is_empty = commit_ras.is_empty 202 val commit_is_full = commit_ras.is_full 203 val commit_top_addr = commit_ras.top_addr 204 205 commit_push := !commit_is_full && io.recover.valid && !io.recover.bits.isReplay && io.recover.bits.pd.isCall 206 commit_pop := !commit_is_empty && io.recover.valid && !io.recover.bits.isReplay && io.recover.bits.pd.isRet 207 208 209 io.out.valid := !spec_is_empty 210 io.out.bits.target := spec_top_addr 211 // TODO: back-up stack for ras 212 // use checkpoint to recover RAS 213 214 val copy_valid = io.recover.valid && (io.recover.bits.isMisPred || io.recover.bits.isReplay) 215 val copy_next = RegNext(copy_valid) 216 spec_ras.copy_valid := copy_next 217 spec_ras.copy_in_mem := commit_ras.copy_out_mem 218 spec_ras.copy_in_sp := commit_ras.copy_out_sp 219 spec_ras.copy_in_top := commit_ras.copy_out_top 220 commit_ras.copy_valid := false.B 221 commit_ras.copy_in_mem := DontCare 222 commit_ras.copy_in_sp := DontCare 223 commit_ras.copy_in_top := DontCare 224 225 //no need to pass the ras branchInfo 226 io.meta.rasSp := DontCare 227 io.meta.rasTopCtr := DontCare 228 io.meta.rasToqAddr := DontCare 229 230 if (!env.FPGAPlatform && env.EnablePerfDebug) { 231 val rasAns = Wire(new PredictorAnswer) 232 rasAns.hit := io.out.valid 233 rasAns.taken := DontCare 234 rasAns.target := io.out.bits.target 235 236 ExcitingUtils.addSource(rasAns, "rasAns") 237 } 238 239 if (BPUDebug && debug) { 240 val spec_debug = spec.debugIO 241 val commit_debug = commit.debugIO 242 XSDebug("----------------RAS(spec)----------------\n") 243 XSDebug(" index addr ctr \n") 244 for(i <- 0 until RasSize){ 245 XSDebug(" (%d) 0x%x %d",i.U,spec_ras.copy_out_mem(i).retAddr,spec_ras.copy_out_mem(i).ctr) 246 when(i.U === spec_ras.copy_out_sp){XSDebug(false,true.B," <----sp")} 247 XSDebug(false,true.B,"\n") 248 } 249 XSDebug("----------------RAS(commit)----------------\n") 250 XSDebug(" index addr ctr \n") 251 for(i <- 0 until RasSize){ 252 XSDebug(" (%d) 0x%x %d",i.U,commit_ras.copy_out_mem(i).retAddr,commit_ras.copy_out_mem(i).ctr) 253 when(i.U === commit_ras.copy_out_sp){XSDebug(false,true.B," <----sp")} 254 XSDebug(false,true.B,"\n") 255 } 256 257 XSDebug(spec_push, "(spec_ras)push inAddr: 0x%x inCtr: %d | allocNewEntry:%d | sp:%d | TopReg.addr %x ctr:%d\n",spec_new_addr,spec_debug.write_entry.ctr,spec_debug.alloc_new,spec_debug.sp.asUInt,spec_debug.topRegister.retAddr,spec_debug.topRegister.ctr) 258 XSDebug(spec_pop, "(spec_ras)pop outValid:%d outAddr: 0x%x \n",io.out.valid,io.out.bits.target) 259 XSDebug(commit_push, "(commit_ras)push inAddr: 0x%x inCtr: %d | allocNewEntry:%d | sp:%d | TopReg.addr %x ctr:%d\n",commit_new_addr,commit_debug.write_entry.ctr,commit_debug.alloc_new,commit_debug.sp.asUInt,commit_debug.topRegister.retAddr,commit_debug.topRegister.ctr) 260 XSDebug(commit_pop, "(commit_ras)pop outValid:%d outAddr: 0x%x \n",io.out.valid,io.out.bits.target) 261 XSDebug("copyValid:%d copyNext:%d \n",copy_valid,copy_next) 262 } 263 264 265 // val recoverSp = io.recover.bits.brInfo.rasSp 266 // val recoverCtr = io.recover.bits.brInfo.rasTopCtr 267 // val recoverAddr = io.recover.bits.brInfo.rasToqAddr 268 // val recover_top = ras(recoverSp - 1.U) 269 // when (recover_valid) { 270 // sp := recoverSp 271 // recover_top.ctr := recoverCtr 272 // recover_top.retAddr := recoverAddr 273 // XSDebug("RAS update: SP:%d , Ctr:%d \n",recoverSp,recoverCtr) 274 // } 275 // val recover_and_push = recover_valid && push 276 // val recover_and_pop = recover_valid && pop 277 // val recover_alloc_new = new_addr =/= recoverAddr 278 // when(recover_and_push) 279 // { 280 // when(recover_alloc_new){ 281 // sp := recoverSp + 1.U 282 // ras(recoverSp).retAddr := new_addr 283 // ras(recoverSp).ctr := 1.U 284 // recover_top.retAddr := recoverAddr 285 // recover_top.ctr := recoverCtr 286 // } .otherwise{ 287 // sp := recoverSp 288 // recover_top.ctr := recoverCtr + 1.U 289 // recover_top.retAddr := recoverAddr 290 // } 291 // } .elsewhen(recover_and_pop) 292 // { 293 // io.out.bits.target := recoverAddr 294 // when ( recover_top.ctr === 1.U) { 295 // sp := recoverSp - 1.U 296 // }.otherwise { 297 // sp := recoverSp 298 // recover_top.ctr := recoverCtr - 1.U 299 // } 300 // } 301 302} 303