xref: /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala (revision 8b33cd30e0034914b58520e0dc3c0c4b1aad6a03) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15*
16*
17* Acknowledgement
18*
19* This implementation is inspired by several key papers:
20* [1] Richard Kessler. "[The alpha 21264 microprocessor.](https://doi.org/10.1109/40.755465)" IEEE Micro 19.2: 24-36.
21* 1999.
22***************************************************************************************/
23
24package xiangshan.mem.mdp
25
26import org.chipsalliance.cde.config.Parameters
27import chisel3._
28import chisel3.util._
29import xiangshan._
30import utils._
31import utility._
32
33// 21264-like wait table, uses 2-bit counter
34class WaitTable(implicit p: Parameters) extends XSModule {
35  val io = IO(new Bundle {
36    // to decode
37    val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // decode pc(VaddrBits-1, 1)
38    val rdata = Vec(DecodeWidth, Output(Bool())) // loadWaitBit
39    val update = Input(new MemPredUpdateReq) // RegNext should be added outside
40    val csrCtrl = Input(new CustomCSRCtrlIO)
41  })
42
43  require(DecodeWidth == RenameWidth)
44
45  val data = RegInit(VecInit(Seq.fill(WaitTableSize)(0.U(2.W))))
46  val resetCounter = RegInit(0.U(ResetTimeMax2Pow.W))
47  resetCounter := resetCounter + 1.U
48
49  // read ports
50  for (i <- 0 until DecodeWidth) {
51    io.rdata(i) := (data(io.raddr(i))(LWTUse2BitCounter.B.asUInt) || io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
52  }
53
54  // write port
55  when(io.update.valid){
56    data(io.update.waddr) := Cat(data(io.update.waddr)(0), true.B)
57  }
58
59  // reset period: ResetTimeMax2Pow
60  when(resetCounter(ResetTimeMax2Pow-1, ResetTimeMin2Pow)(RegNext(io.csrCtrl.lvpred_timeout))) {
61    for (j <- 0 until WaitTableSize) {
62      data(j) := 0.U
63    }
64    resetCounter:= 0.U
65  }
66
67  // debug
68  XSDebug(io.update.valid, "%d: waittable update: pc %x data: %x\n", GTimer(), io.update.waddr, io.update.wdata)
69
70  XSPerfAccumulate("wait_table_bit_set", PopCount(data.map(d => d(1))))
71}
72