1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIOWithVaddr, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 26import difftest._ 27import xiangshan.ExceptionNO._ 28import xiangshan.backend.fu.PMPRespBundle 29 30class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 31 val io = IO(new Bundle() { 32 val hartId = Input(UInt(8.W)) 33 val in = Flipped(Decoupled(new ExuInput)) 34 val storeDataIn = Flipped(Valid(new ExuOutput)) // src2 from rs 35 val out = Decoupled(new ExuOutput) 36 val dcache = new DCacheWordIOWithVaddr 37 val dtlb = new TlbRequestIO 38 val pmpResp = Flipped(new PMPRespBundle()) 39 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 40 val flush_sbuffer = new SbufferFlushBundle 41 val feedbackSlow = ValidIO(new RSFeedback) 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 44 }) 45 46 //------------------------------------------------------- 47 // Atomics Memory Accsess FSM 48 //------------------------------------------------------- 49 val s_invalid :: s_tlb :: s_pm :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(8) 50 val state = RegInit(s_invalid) 51 val data_valid = RegInit(false.B) 52 val in = Reg(new ExuInput()) 53 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 54 val atom_override_xtval = RegInit(false.B) 55 // paddr after translation 56 val paddr = Reg(UInt()) 57 val is_mmio = Reg(Bool()) 58 // dcache response data 59 val resp_data = Reg(UInt()) 60 val resp_data_wire = WireInit(0.U) 61 val is_lrsc_valid = Reg(Bool()) 62 63 // Difftest signals 64 val paddr_reg = Reg(UInt(64.W)) 65 val data_reg = Reg(UInt(64.W)) 66 val mask_reg = Reg(UInt(8.W)) 67 val fuop_reg = Reg(UInt(8.W)) 68 69 io.exceptionAddr.valid := atom_override_xtval 70 io.exceptionAddr.bits := in.src(0) 71 72 // assign default value to output signals 73 io.in.ready := false.B 74 io.out.valid := false.B 75 io.out.bits := DontCare 76 77 io.dcache.req.valid := false.B 78 io.dcache.req.bits := DontCare 79 io.dcache.resp.ready := false.B 80 81 io.dtlb.req.valid := false.B 82 io.dtlb.req.bits := DontCare 83 io.dtlb.resp.ready := false.B 84 85 io.flush_sbuffer.valid := false.B 86 87 XSDebug("state: %d\n", state) 88 89 when (state === s_invalid) { 90 io.in.ready := true.B 91 when (io.in.fire()) { 92 in := io.in.bits 93 in.src(1) := in.src(1) // leave src2 unchanged 94 state := s_tlb 95 } 96 } 97 98 when (io.storeDataIn.fire()) { 99 in.src(1) := io.storeDataIn.bits.data 100 data_valid := true.B 101 } 102 103 assert(!(io.storeDataIn.fire() && data_valid), "atomic unit re-receive data") 104 105 // Send TLB feedback to store issue queue 106 // we send feedback right after we receives request 107 // also, we always treat amo as tlb hit 108 // since we will continue polling tlb all by ourself 109 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 110 io.feedbackSlow.bits.hit := true.B 111 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 112 io.feedbackSlow.bits.flushState := DontCare 113 io.feedbackSlow.bits.sourceType := DontCare 114 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 115 116 // tlb translation, manipulating signals && deal with exception 117 when (state === s_tlb) { 118 // send req to dtlb 119 // keep firing until tlb hit 120 io.dtlb.req.valid := true.B 121 io.dtlb.req.bits.vaddr := in.src(0) 122 io.dtlb.req.bits.robIdx := in.uop.robIdx 123 io.dtlb.resp.ready := true.B 124 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 125 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 126 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 127 io.dtlb.req.bits.debug.isFirstIssue := false.B 128 129 when(io.dtlb.resp.fire){ 130 paddr := io.dtlb.resp.bits.paddr 131 // exception handling 132 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 133 "b00".U -> true.B, //b 134 "b01".U -> (in.src(0)(0) === 0.U), //h 135 "b10".U -> (in.src(0)(1,0) === 0.U), //w 136 "b11".U -> (in.src(0)(2,0) === 0.U) //d 137 )) 138 exceptionVec(storeAddrMisaligned) := !addrAligned 139 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 140 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 141 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 142 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 143 144 when (!io.dtlb.resp.bits.miss) { 145 when (!addrAligned) { 146 // NOTE: when addrAligned, do not need to wait tlb actually 147 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 148 // if there are exceptions, no need to execute it 149 state := s_finish 150 atom_override_xtval := true.B 151 } .otherwise { 152 state := s_pm 153 } 154 } 155 } 156 } 157 158 when (state === s_pm) { 159 is_mmio := io.pmpResp.mmio 160 // NOTE: only handle load/store exception here, if other exception happens, don't send here 161 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 162 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 163 val exception_pa = io.pmpResp.st 164 when (exception_va || exception_pa) { 165 state := s_finish 166 atom_override_xtval := true.B 167 }.otherwise { 168 state := s_flush_sbuffer_req 169 } 170 } 171 172 when (state === s_flush_sbuffer_req) { 173 io.flush_sbuffer.valid := true.B 174 state := s_flush_sbuffer_resp 175 } 176 177 when (state === s_flush_sbuffer_resp) { 178 when (io.flush_sbuffer.empty) { 179 state := s_cache_req 180 } 181 } 182 183 when (state === s_cache_req) { 184 io.dcache.req.valid := true.B 185 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 186 LSUOpType.lr_w -> M_XLR, 187 LSUOpType.sc_w -> M_XSC, 188 LSUOpType.amoswap_w -> M_XA_SWAP, 189 LSUOpType.amoadd_w -> M_XA_ADD, 190 LSUOpType.amoxor_w -> M_XA_XOR, 191 LSUOpType.amoand_w -> M_XA_AND, 192 LSUOpType.amoor_w -> M_XA_OR, 193 LSUOpType.amomin_w -> M_XA_MIN, 194 LSUOpType.amomax_w -> M_XA_MAX, 195 LSUOpType.amominu_w -> M_XA_MINU, 196 LSUOpType.amomaxu_w -> M_XA_MAXU, 197 198 LSUOpType.lr_d -> M_XLR, 199 LSUOpType.sc_d -> M_XSC, 200 LSUOpType.amoswap_d -> M_XA_SWAP, 201 LSUOpType.amoadd_d -> M_XA_ADD, 202 LSUOpType.amoxor_d -> M_XA_XOR, 203 LSUOpType.amoand_d -> M_XA_AND, 204 LSUOpType.amoor_d -> M_XA_OR, 205 LSUOpType.amomin_d -> M_XA_MIN, 206 LSUOpType.amomax_d -> M_XA_MAX, 207 LSUOpType.amominu_d -> M_XA_MINU, 208 LSUOpType.amomaxu_d -> M_XA_MAXU 209 )) 210 211 io.dcache.req.bits.addr := paddr 212 io.dcache.req.bits.vaddr := in.src(0) // vaddr 213 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 214 // TODO: atomics do need mask: fix mask 215 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 216 io.dcache.req.bits.id := DontCare 217 218 when(io.dcache.req.fire()){ 219 state := s_cache_resp 220 paddr_reg := io.dcache.req.bits.addr 221 data_reg := io.dcache.req.bits.data 222 mask_reg := io.dcache.req.bits.mask 223 fuop_reg := in.uop.ctrl.fuOpType 224 } 225 } 226 227 when (state === s_cache_resp) { 228 io.dcache.resp.ready := data_valid 229 when(io.dcache.resp.fire()) { 230 is_lrsc_valid := io.dcache.resp.bits.id 231 val rdata = io.dcache.resp.bits.data 232 val rdataSel = LookupTree(paddr(2, 0), List( 233 "b000".U -> rdata(63, 0), 234 "b001".U -> rdata(63, 8), 235 "b010".U -> rdata(63, 16), 236 "b011".U -> rdata(63, 24), 237 "b100".U -> rdata(63, 32), 238 "b101".U -> rdata(63, 40), 239 "b110".U -> rdata(63, 48), 240 "b111".U -> rdata(63, 56) 241 )) 242 243 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 244 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 245 LSUOpType.sc_w -> rdata, 246 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 247 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 248 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 249 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 250 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 251 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 252 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 253 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 254 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 255 256 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 257 LSUOpType.sc_d -> rdata, 258 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 259 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 260 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 261 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 262 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 263 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 264 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 265 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 266 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 267 )) 268 269 resp_data := resp_data_wire 270 state := s_finish 271 } 272 } 273 274 when (state === s_finish) { 275 io.out.valid := true.B 276 io.out.bits.uop := in.uop 277 io.out.bits.uop.cf.exceptionVec := exceptionVec 278 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 279 io.out.bits.data := resp_data 280 io.out.bits.redirectValid := false.B 281 io.out.bits.redirect := DontCare 282 io.out.bits.debug.isMMIO := is_mmio 283 io.out.bits.debug.paddr := paddr 284 when (io.out.fire()) { 285 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 286 state := s_invalid 287 } 288 data_valid := false.B 289 } 290 291 when (io.redirect.valid) { 292 atom_override_xtval := false.B 293 } 294 295 if (env.EnableDifftest) { 296 val difftest = Module(new DifftestAtomicEvent) 297 difftest.io.clock := clock 298 difftest.io.coreid := io.hartId 299 difftest.io.atomicResp := io.dcache.resp.fire() 300 difftest.io.atomicAddr := paddr_reg 301 difftest.io.atomicData := data_reg 302 difftest.io.atomicMask := mask_reg 303 difftest.io.atomicFuop := fuop_reg 304 difftest.io.atomicOut := resp_data_wire 305 } 306} 307