feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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fix(AtomicsUnit): flush sbuffer until sbuffer is empty (#4487)

In the previous design, AtomicsUnit sends out sbuffer flush request only
under `s_tlb_and_flush_sbuffer_req` state. The request sets sb

fix(AtomicsUnit): flush sbuffer until sbuffer is empty (#4487)

In the previous design, AtomicsUnit sends out sbuffer flush request only
under `s_tlb_and_flush_sbuffer_req` state. The request sets sbuffer
under `x_drain_all` state. Sbuffer returns to `x_idle` state when it is
empty. However StoreQueue may not be fully cleared at this point because
there could be committed stores that haven't yet entered sbuffer. After
these stores eventually enter sbuffer, sbuffer remains in `x_idle` state
and will not flush them into DCache. This results in sbuffer being
unable to drain completely, therefore the atomic instruction gets into
deadlock.

This commit fixes this bug by continuously request sbuffer flush until
sbuffer is fully drained.

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style(Bundles): move bundles to Bundles.scala (#4247)

fix(AtomicsUnit): atomic access on uncache should raise af (#4214)

Atomic access on uncache or MMIO region is not supported for now. The
previous design did not consider exception handling for atomi

fix(AtomicsUnit): atomic access on uncache should raise af (#4214)

Atomic access on uncache or MMIO region is not supported for now. The
previous design did not consider exception handling for atomic
instructions with PBMT=NC.

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feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(Backend): add support for Zacas extension

misc: remove assert temporarily

feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

fix(NC): fix a list of bugs of NC WMO access

* fix(PBMT): skip nc difftest and handle the conflict of nc and normal store

* fix(PBMT): nc st req is changed to a state machine execution

* fix(pbmt)

fix(NC): fix a list of bugs of NC WMO access

* fix(PBMT): skip nc difftest and handle the conflict of nc and normal store

* fix(PBMT): nc st req is changed to a state machine execution

* fix(pbmt): fix typo and control error of nc ld

* fix(pbmt): nc data assignment error

* fix(pbmt): nc should be used to wakeup

* fix(pbmt): remove wrong assert

* fix(pbmt): lots of bugs of nc st ld forward

* fix(pbmt): fix address align error

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area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType'

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType', reassign the value when writeback Rob in pipeline,
so no longer saved in LSQ.
3. optimise 'uop.imm', vaddr is computed in StoreMisalignBuffer and
there is no need to store the uop.imm.

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style(AtomicsUnit): remove unnecessary logics (#3836)

Atomics memory operations only work on word, double word and quad word
in the future. Therefore any code concerning byte and half word is
redu

style(AtomicsUnit): remove unnecessary logics (#3836)

Atomics memory operations only work on word, double word and quad word
in the future. Therefore any code concerning byte and half word is
redundant and only contributes to worse timing and area.

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fix(AtomicsUnit): Assert `atom_override_xtval` when trigger fire. (#3803)

fix(trigger): move trigger checking to `s_tlb_and_flush_sbuffer_req` in AtomicsUnit (#3712)

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(AtomicsUnit) : mmio address should report access fault (#3443)

Trigger: refactor trigger information in pipeline. (#3403)

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172)

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: CharlieLiu <[email protected]>

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LSU, RVH: fix the bug about the exception vaddr of guest page fault (#2898)

After new backend was merged into master, the guest page fault was
delete from fuConfig. That results in the wrong guest

LSU, RVH: fix the bug about the exception vaddr of guest page fault (#2898)

After new backend was merged into master, the guest page fault was
delete from fuConfig. That results in the wrong guest page fault
exception vaddr in CSR module. This commit adds gpf back to fuConfig

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Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: rewrite the logic of getting gpaddr when guest page fault

RVH: fix AMO Guest page fault problem
AtomicsUnit forgets to handle Guest Page Fault at state s_pm, which causes access to DCache and an assertion fail.

RVH: finish the desigh of H extention