1package xiangshan.mem 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 9import difftest._ 10 11class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 12 val io = IO(new Bundle() { 13 val in = Flipped(Decoupled(new ExuInput)) 14 val storeDataIn = Flipped(Valid(new StoreDataBundle)) // src2 from rs 15 val out = Decoupled(new ExuOutput) 16 val dcache = new DCacheWordIO 17 val dtlb = new TlbRequestIO 18 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 19 val flush_sbuffer = new SbufferFlushBundle 20 val rsFeedback = ValidIO(new RSFeedback) 21 val redirect = Flipped(ValidIO(new Redirect)) 22 val flush = Input(Bool()) 23 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 24 }) 25 26 //------------------------------------------------------- 27 // Atomics Memory Accsess FSM 28 //------------------------------------------------------- 29 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 30 val state = RegInit(s_invalid) 31 val addr_valid = RegInit(false.B) 32 val data_valid = RegInit(false.B) 33 val in = Reg(new ExuInput()) 34 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 35 val atom_override_xtval = RegInit(false.B) 36 // paddr after translation 37 val paddr = Reg(UInt()) 38 val is_mmio = Reg(Bool()) 39 // dcache response data 40 val resp_data = Reg(UInt()) 41 val resp_data_wire = WireInit(0.U) 42 val is_lrsc_valid = Reg(Bool()) 43 44 // Difftest signals 45 val paddr_reg = Reg(UInt(64.W)) 46 val data_reg = Reg(UInt(64.W)) 47 val mask_reg = Reg(UInt(8.W)) 48 val fuop_reg = Reg(UInt(8.W)) 49 50 io.exceptionAddr.valid := atom_override_xtval 51 io.exceptionAddr.bits := in.src(0) 52 53 // assign default value to output signals 54 io.in.ready := false.B 55 io.out.valid := false.B 56 io.out.bits := DontCare 57 58 io.dcache.req.valid := false.B 59 io.dcache.req.bits := DontCare 60 io.dcache.resp.ready := false.B 61 62 io.dtlb.req.valid := false.B 63 io.dtlb.req.bits := DontCare 64 io.dtlb.resp.ready := false.B 65 66 io.flush_sbuffer.valid := false.B 67 68 XSDebug("state: %d\n", state) 69 70 when (state === s_invalid) { 71 io.in.ready := true.B 72 when (io.in.fire()) { 73 in := io.in.bits 74 in.src(1) := in.src(1) // leave src2 unchanged 75 addr_valid := true.B 76 } 77 when (io.storeDataIn.fire()) { 78 in.src(1) := io.storeDataIn.bits.data 79 data_valid := true.B 80 } 81 when(data_valid && addr_valid) { 82 state := s_tlb 83 addr_valid := false.B 84 data_valid := false.B 85 } 86 } 87 88 89 // Send TLB feedback to store issue queue 90 // we send feedback right after we receives request 91 // also, we always treat amo as tlb hit 92 // since we will continue polling tlb all by ourself 93 io.rsFeedback.valid := RegNext(RegNext(io.in.valid)) 94 io.rsFeedback.bits.hit := true.B 95 io.rsFeedback.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 96 io.rsFeedback.bits.flushState := DontCare 97 io.rsFeedback.bits.sourceType := DontCare 98 99 // tlb translation, manipulating signals && deal with exception 100 when (state === s_tlb) { 101 // send req to dtlb 102 // keep firing until tlb hit 103 io.dtlb.req.valid := true.B 104 io.dtlb.req.bits.vaddr := in.src(0) 105 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 106 io.dtlb.resp.ready := true.B 107 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 108 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 109 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 110 io.dtlb.req.bits.debug.isFirstIssue := false.B 111 112 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 113 // exception handling 114 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 115 "b00".U -> true.B, //b 116 "b01".U -> (in.src(0)(0) === 0.U), //h 117 "b10".U -> (in.src(0)(1,0) === 0.U), //w 118 "b11".U -> (in.src(0)(2,0) === 0.U) //d 119 )) 120 exceptionVec(storeAddrMisaligned) := !addrAligned 121 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 122 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 123 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 124 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 125 val exception = !addrAligned || 126 io.dtlb.resp.bits.excp.pf.st || 127 io.dtlb.resp.bits.excp.pf.ld || 128 io.dtlb.resp.bits.excp.af.st || 129 io.dtlb.resp.bits.excp.af.ld 130 is_mmio := io.dtlb.resp.bits.mmio 131 when (exception) { 132 // check for exceptions 133 // if there are exceptions, no need to execute it 134 state := s_finish 135 atom_override_xtval := true.B 136 } .otherwise { 137 paddr := io.dtlb.resp.bits.paddr 138 state := s_flush_sbuffer_req 139 } 140 } 141 } 142 143 144 when (state === s_flush_sbuffer_req) { 145 io.flush_sbuffer.valid := true.B 146 state := s_flush_sbuffer_resp 147 } 148 149 when (state === s_flush_sbuffer_resp) { 150 when (io.flush_sbuffer.empty) { 151 state := s_cache_req 152 } 153 } 154 155 when (state === s_cache_req) { 156 io.dcache.req.valid := true.B 157 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 158 LSUOpType.lr_w -> M_XLR, 159 LSUOpType.sc_w -> M_XSC, 160 LSUOpType.amoswap_w -> M_XA_SWAP, 161 LSUOpType.amoadd_w -> M_XA_ADD, 162 LSUOpType.amoxor_w -> M_XA_XOR, 163 LSUOpType.amoand_w -> M_XA_AND, 164 LSUOpType.amoor_w -> M_XA_OR, 165 LSUOpType.amomin_w -> M_XA_MIN, 166 LSUOpType.amomax_w -> M_XA_MAX, 167 LSUOpType.amominu_w -> M_XA_MINU, 168 LSUOpType.amomaxu_w -> M_XA_MAXU, 169 170 LSUOpType.lr_d -> M_XLR, 171 LSUOpType.sc_d -> M_XSC, 172 LSUOpType.amoswap_d -> M_XA_SWAP, 173 LSUOpType.amoadd_d -> M_XA_ADD, 174 LSUOpType.amoxor_d -> M_XA_XOR, 175 LSUOpType.amoand_d -> M_XA_AND, 176 LSUOpType.amoor_d -> M_XA_OR, 177 LSUOpType.amomin_d -> M_XA_MIN, 178 LSUOpType.amomax_d -> M_XA_MAX, 179 LSUOpType.amominu_d -> M_XA_MINU, 180 LSUOpType.amomaxu_d -> M_XA_MAXU 181 )) 182 183 io.dcache.req.bits.addr := paddr 184 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 185 // TODO: atomics do need mask: fix mask 186 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 187 io.dcache.req.bits.id := DontCare 188 189 when(io.dcache.req.fire()){ 190 state := s_cache_resp 191 paddr_reg := io.dcache.req.bits.addr 192 data_reg := io.dcache.req.bits.data 193 mask_reg := io.dcache.req.bits.mask 194 fuop_reg := in.uop.ctrl.fuOpType 195 } 196 } 197 198 when (state === s_cache_resp) { 199 io.dcache.resp.ready := true.B 200 when(io.dcache.resp.fire()) { 201 is_lrsc_valid := io.dcache.resp.bits.id 202 val rdata = io.dcache.resp.bits.data 203 val rdataSel = LookupTree(paddr(2, 0), List( 204 "b000".U -> rdata(63, 0), 205 "b001".U -> rdata(63, 8), 206 "b010".U -> rdata(63, 16), 207 "b011".U -> rdata(63, 24), 208 "b100".U -> rdata(63, 32), 209 "b101".U -> rdata(63, 40), 210 "b110".U -> rdata(63, 48), 211 "b111".U -> rdata(63, 56) 212 )) 213 214 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 215 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 216 LSUOpType.sc_w -> rdata, 217 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 218 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 219 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 220 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 221 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 222 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 223 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 224 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 225 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 226 227 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 228 LSUOpType.sc_d -> rdata, 229 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 230 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 231 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 232 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 233 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 234 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 235 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 236 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 237 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 238 )) 239 240 resp_data := resp_data_wire 241 state := s_finish 242 } 243 } 244 245 when (state === s_finish) { 246 io.out.valid := true.B 247 io.out.bits.uop := in.uop 248 io.out.bits.uop.cf.exceptionVec := exceptionVec 249 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 250 io.out.bits.data := resp_data 251 io.out.bits.redirectValid := false.B 252 io.out.bits.redirect := DontCare 253 io.out.bits.debug.isMMIO := is_mmio 254 io.out.bits.debug.paddr := paddr 255 when (io.out.fire()) { 256 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 257 state := s_invalid 258 } 259 } 260 261 when(io.redirect.valid || io.flush){ 262 atom_override_xtval := false.B 263 } 264 265 if (!env.FPGAPlatform) { 266 val difftest = Module(new DifftestAtomicEvent) 267 difftest.io.clock := clock 268 difftest.io.coreid := hardId.U 269 difftest.io.atomicResp := io.dcache.resp.fire() 270 difftest.io.atomicAddr := paddr_reg 271 difftest.io.atomicData := data_reg 272 difftest.io.atomicMask := mask_reg 273 difftest.io.atomicFuop := fuop_reg 274 difftest.io.atomicOut := resp_data_wire 275 } 276} 277