1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, HasDCacheParameters, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 31import xiangshan.backend.fu.util.SdtrigExt 32 33class AtomicsUnit(implicit p: Parameters) extends XSModule 34 with MemoryOpConstants 35 with HasDCacheParameters 36 with SdtrigExt{ 37 val io = IO(new Bundle() { 38 val hartId = Input(UInt(hartIdLen.W)) 39 val in = Flipped(Decoupled(new MemExuInput)) 40 val storeDataIn = Flipped(Valid(new MemExuOutput)) // src2 from rs 41 val out = Decoupled(new MemExuOutput) 42 val dcache = new AtomicWordIO 43 val dtlb = new TlbRequestIO(2) 44 val pmpResp = Flipped(new PMPRespBundle()) 45 val flush_sbuffer = new SbufferFlushBundle 46 val feedbackSlow = ValidIO(new RSFeedback) 47 val redirect = Flipped(ValidIO(new Redirect)) 48 val exceptionAddr = ValidIO(new Bundle { 49 val vaddr = UInt(VAddrBits.W) 50 val gpaddr = UInt(GPAddrBits.W) 51 }) 52 val csrCtrl = Flipped(new CustomCSRCtrlIO) 53 }) 54 55 //------------------------------------------------------- 56 // Atomics Memory Accsess FSM 57 //------------------------------------------------------- 58 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 59 val state = RegInit(s_invalid) 60 val out_valid = RegInit(false.B) 61 val data_valid = RegInit(false.B) 62 val in = Reg(new MemExuInput()) 63 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 64 val atom_override_xtval = RegInit(false.B) 65 val have_sent_first_tlb_req = RegInit(false.B) 66 val isLr = in.uop.fuOpType === LSUOpType.lr_w || in.uop.fuOpType === LSUOpType.lr_d 67 // paddr after translation 68 val paddr = Reg(UInt()) 69 val gpaddr = Reg(UInt()) 70 val vaddr = in.src(0) 71 val is_mmio = Reg(Bool()) 72 73 // dcache response data 74 val resp_data = Reg(UInt()) 75 val resp_data_wire = WireInit(0.U) 76 val is_lrsc_valid = Reg(Bool()) 77 // sbuffer is empty or not 78 val sbuffer_empty = io.flush_sbuffer.empty 79 80 81 // Difftest signals 82 val paddr_reg = Reg(UInt(64.W)) 83 val data_reg = Reg(UInt(64.W)) 84 val mask_reg = Reg(UInt(8.W)) 85 val fuop_reg = Reg(UInt(8.W)) 86 87 io.exceptionAddr.valid := atom_override_xtval 88 io.exceptionAddr.bits.vaddr := in.src(0) 89 io.exceptionAddr.bits.gpaddr := gpaddr 90 91 // assign default value to output signals 92 io.in.ready := false.B 93 94 io.dcache.req.valid := false.B 95 io.dcache.req.bits := DontCare 96 97 io.dtlb.req.valid := false.B 98 io.dtlb.req.bits := DontCare 99 io.dtlb.req_kill := false.B 100 io.dtlb.resp.ready := true.B 101 102 io.flush_sbuffer.valid := false.B 103 104 XSDebug("state: %d\n", state) 105 106 when (state === s_invalid) { 107 io.in.ready := true.B 108 when (io.in.fire) { 109 in := io.in.bits 110 in.src(1) := in.src(1) // leave src2 unchanged 111 state := s_tlb_and_flush_sbuffer_req 112 have_sent_first_tlb_req := false.B 113 } 114 } 115 116 when (io.storeDataIn.fire) { 117 in.src(1) := io.storeDataIn.bits.data 118 data_valid := true.B 119 } 120 121 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 122 123 // Send TLB feedback to store issue queue 124 // we send feedback right after we receives request 125 // also, we always treat amo as tlb hit 126 // since we will continue polling tlb all by ourself 127 io.feedbackSlow.valid := GatedValidRegNext(GatedValidRegNext(io.in.valid)) 128 io.feedbackSlow.bits.hit := true.B 129 io.feedbackSlow.bits.robIdx := RegEnable(io.in.bits.uop.robIdx, io.in.valid) 130 io.feedbackSlow.bits.sqIdx := RegEnable(io.in.bits.uop.sqIdx, io.in.valid) 131 io.feedbackSlow.bits.flushState := DontCare 132 io.feedbackSlow.bits.sourceType := DontCare 133 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 134 135 // tlb translation, manipulating signals && deal with exception 136 // at the same time, flush sbuffer 137 when (state === s_tlb_and_flush_sbuffer_req) { 138 // send req to dtlb 139 // keep firing until tlb hit 140 io.dtlb.req.valid := true.B 141 io.dtlb.req.bits.vaddr := in.src(0) 142 io.dtlb.resp.ready := true.B 143 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 144 io.dtlb.req.bits.debug.pc := in.uop.pc 145 io.dtlb.req.bits.debug.robIdx := in.uop.robIdx 146 io.dtlb.req.bits.debug.isFirstIssue := false.B 147 io.out.bits.uop.debugInfo.tlbFirstReqTime := GTimer() // FIXME lyq: it will be always assigned 148 149 // send req to sbuffer to flush it if it is not empty 150 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 151 152 // do not accept tlb resp in the first cycle 153 // this limition is for hw prefetcher 154 // when !have_sent_first_tlb_req, tlb resp may come from hw prefetch 155 have_sent_first_tlb_req := true.B 156 157 when(io.dtlb.resp.fire && have_sent_first_tlb_req){ 158 paddr := io.dtlb.resp.bits.paddr(0) 159 gpaddr := io.dtlb.resp.bits.gpaddr(0) 160 // exception handling 161 val addrAligned = LookupTree(in.uop.fuOpType(1,0), List( 162 "b00".U -> true.B, //b 163 "b01".U -> (in.src(0)(0) === 0.U), //h 164 "b10".U -> (in.src(0)(1,0) === 0.U), //w 165 "b11".U -> (in.src(0)(2,0) === 0.U) //d 166 )) 167 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 168 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 169 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 170 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 171 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 172 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 173 exceptionVec(storeGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.st 174 exceptionVec(loadGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.ld 175 176 when (!io.dtlb.resp.bits.miss) { 177 io.out.bits.uop.debugInfo.tlbRespTime := GTimer() 178 when (!addrAligned) { 179 // NOTE: when addrAligned, do not need to wait tlb actually 180 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 181 // if there are exceptions, no need to execute it 182 state := s_finish 183 out_valid := true.B 184 atom_override_xtval := true.B 185 } .otherwise { 186 state := s_pm 187 } 188 } 189 } 190 } 191 192 when (state === s_pm) { 193 val pmp = WireInit(io.pmpResp) 194 is_mmio := pmp.mmio 195 196 // NOTE: only handle load/store exception here, if other exception happens, don't send here 197 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 198 exceptionVec(storeGuestPageFault) || exceptionVec(loadGuestPageFault) || 199 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 200 val exception_pa = pmp.st || pmp.ld 201 when (exception_va || exception_pa) { 202 state := s_finish 203 out_valid := true.B 204 atom_override_xtval := true.B 205 }.otherwise { 206 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 207 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 208 } 209 // update storeAccessFault bit 210 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || pmp.ld && isLr 211 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || pmp.ld && !isLr 212 } 213 214 when (state === s_wait_flush_sbuffer_resp) { 215 when (sbuffer_empty) { 216 state := s_cache_req 217 } 218 } 219 220 when (state === s_cache_req) { 221 val pipe_req = io.dcache.req.bits 222 pipe_req := DontCare 223 224 pipe_req.cmd := LookupTree(in.uop.fuOpType, List( 225 LSUOpType.lr_w -> M_XLR, 226 LSUOpType.sc_w -> M_XSC, 227 LSUOpType.amoswap_w -> M_XA_SWAP, 228 LSUOpType.amoadd_w -> M_XA_ADD, 229 LSUOpType.amoxor_w -> M_XA_XOR, 230 LSUOpType.amoand_w -> M_XA_AND, 231 LSUOpType.amoor_w -> M_XA_OR, 232 LSUOpType.amomin_w -> M_XA_MIN, 233 LSUOpType.amomax_w -> M_XA_MAX, 234 LSUOpType.amominu_w -> M_XA_MINU, 235 LSUOpType.amomaxu_w -> M_XA_MAXU, 236 237 LSUOpType.lr_d -> M_XLR, 238 LSUOpType.sc_d -> M_XSC, 239 LSUOpType.amoswap_d -> M_XA_SWAP, 240 LSUOpType.amoadd_d -> M_XA_ADD, 241 LSUOpType.amoxor_d -> M_XA_XOR, 242 LSUOpType.amoand_d -> M_XA_AND, 243 LSUOpType.amoor_d -> M_XA_OR, 244 LSUOpType.amomin_d -> M_XA_MIN, 245 LSUOpType.amomax_d -> M_XA_MAX, 246 LSUOpType.amominu_d -> M_XA_MINU, 247 LSUOpType.amomaxu_d -> M_XA_MAXU 248 )) 249 pipe_req.miss := false.B 250 pipe_req.probe := false.B 251 pipe_req.probe_need_data := false.B 252 pipe_req.source := AMO_SOURCE.U 253 pipe_req.addr := get_block_addr(paddr) 254 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 255 pipe_req.word_idx := get_word(paddr) 256 pipe_req.amo_data := genWdata(in.src(1), in.uop.fuOpType(1,0)) 257 pipe_req.amo_mask := genWmask(paddr, in.uop.fuOpType(1,0)) 258 259 io.dcache.req.valid := Mux( 260 io.dcache.req.bits.cmd === M_XLR, 261 !io.dcache.block_lr, // block lr to survive in lr storm 262 data_valid // wait until src(1) is ready 263 ) 264 265 when(io.dcache.req.fire){ 266 state := s_cache_resp 267 paddr_reg := paddr 268 data_reg := io.dcache.req.bits.amo_data 269 mask_reg := io.dcache.req.bits.amo_mask 270 fuop_reg := in.uop.fuOpType 271 } 272 } 273 274 val dcache_resp_data = Reg(UInt()) 275 val dcache_resp_id = Reg(UInt()) 276 val dcache_resp_error = Reg(Bool()) 277 278 when (state === s_cache_resp) { 279 // when not miss 280 // everything is OK, simply send response back to sbuffer 281 // when miss and not replay 282 // wait for missQueue to handling miss and replaying our request 283 // when miss and replay 284 // req missed and fail to enter missQueue, manually replay it later 285 // TODO: add assertions: 286 // 1. add a replay delay counter? 287 // 2. when req gets into MissQueue, it should not miss any more 288 when(io.dcache.resp.fire) { 289 when(io.dcache.resp.bits.miss) { 290 when(io.dcache.resp.bits.replay) { 291 state := s_cache_req 292 } 293 } .otherwise { 294 dcache_resp_data := io.dcache.resp.bits.data 295 dcache_resp_id := io.dcache.resp.bits.id 296 dcache_resp_error := io.dcache.resp.bits.error 297 state := s_cache_resp_latch 298 } 299 } 300 } 301 302 when (state === s_cache_resp_latch) { 303 is_lrsc_valid := dcache_resp_id 304 val rdataSel = LookupTree(paddr(2, 0), List( 305 "b000".U -> dcache_resp_data(63, 0), 306 "b001".U -> dcache_resp_data(63, 8), 307 "b010".U -> dcache_resp_data(63, 16), 308 "b011".U -> dcache_resp_data(63, 24), 309 "b100".U -> dcache_resp_data(63, 32), 310 "b101".U -> dcache_resp_data(63, 40), 311 "b110".U -> dcache_resp_data(63, 48), 312 "b111".U -> dcache_resp_data(63, 56) 313 )) 314 315 resp_data_wire := LookupTree(in.uop.fuOpType, List( 316 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 317 LSUOpType.sc_w -> dcache_resp_data, 318 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 319 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 320 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 321 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 322 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 323 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 324 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 325 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 326 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 327 328 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 329 LSUOpType.sc_d -> dcache_resp_data, 330 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 331 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 332 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 333 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 334 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 335 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 336 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 337 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 338 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 339 )) 340 341 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 342 exceptionVec(loadAccessFault) := isLr 343 exceptionVec(storeAccessFault) := !isLr 344 assert(!exceptionVec(loadAccessFault)) 345 assert(!exceptionVec(storeAccessFault)) 346 } 347 348 resp_data := resp_data_wire 349 state := s_finish 350 out_valid := true.B 351 } 352 353 io.out.valid := out_valid 354 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 355 io.out.bits := DontCare 356 io.out.bits.uop := in.uop 357 io.out.bits.uop.exceptionVec := exceptionVec 358 io.out.bits.data := resp_data 359 io.out.bits.debug.isMMIO := is_mmio 360 io.out.bits.debug.paddr := paddr 361 when (io.out.fire) { 362 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.pc, io.dcache.resp.bits.data) 363 state := s_invalid 364 out_valid := false.B 365 } 366 367 when (state === s_finish) { 368 data_valid := false.B 369 } 370 371 when (io.redirect.valid) { 372 atom_override_xtval := false.B 373 } 374 375 /* 376 // atomic trigger 377 val csrCtrl = io.csrCtrl 378 val tdata = Reg(Vec(TriggerNum, new MatchTriggerIO)) 379 val tEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 380 tEnableVec := csrCtrl.mem_trigger.tEnableVec 381 when(csrCtrl.mem_trigger.tUpdate.valid) { 382 tdata(csrCtrl.mem_trigger.tUpdate.bits.addr) := csrCtrl.mem_trigger.tUpdate.bits.tdata 383 } 384 385 val backendTriggerTimingVec = VecInit(tdata.map(_.timing)) 386 val backendTriggerChainVec = VecInit(tdata.map(_.chain)) 387 val backendTriggerHitVec = WireInit(VecInit(Seq.fill(TriggerNum)(false.B))) 388 val backendTriggerCanFireVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 389 390 when(state === s_cache_req) { 391 // store trigger 392 val store_hit = Wire(Vec(TriggerNum, Bool())) 393 for (j <- 0 until TriggerNum) { 394 store_hit(j) := !tdata(j).select && TriggerCmp( 395 vaddr, 396 tdata(j).tdata2, 397 tdata(j).matchType, 398 tEnableVec(j) && tdata(j).store 399 ) 400 } 401 // load trigger 402 val load_hit = Wire(Vec(TriggerNum, Bool())) 403 for (j <- 0 until TriggerNum) { 404 load_hit(j) := !tdata(j).select && TriggerCmp( 405 vaddr, 406 tdata(j).tdata2, 407 tdata(j).matchType, 408 tEnableVec(j) && tdata(j).load 409 ) 410 } 411 backendTriggerHitVec := store_hit.zip(load_hit).map { case (sh, lh) => sh || lh } 412 // triggerCanFireVec will update at T+1 413 TriggerCheckCanFire(TriggerNum, backendTriggerCanFireVec, backendTriggerHitVec, backendTriggerTimingVec, backendTriggerChainVec) 414 } 415 416 // addr trigger do cmp at s_cache_req 417 // trigger result is used at s_finish 418 // thus we can delay it safely 419 io.out.bits.uop.trigger.backendHit := backendTriggerHitVec 420 io.out.bits.uop.trigger.backendCanFire := backendTriggerCanFireVec 421 422 */ 423 424 if (env.EnableDifftest) { 425 val difftest = DifftestModule(new DiffAtomicEvent) 426 difftest.coreid := io.hartId 427 difftest.valid := state === s_cache_resp_latch 428 difftest.addr := paddr_reg 429 difftest.data := data_reg 430 difftest.mask := mask_reg 431 difftest.fuop := fuop_reg 432 difftest.out := resp_data_wire 433 } 434 435 if (env.EnableDifftest || env.AlwaysBasicDiff) { 436 val uop = io.out.bits.uop 437 val difftest = DifftestModule(new DiffLrScEvent) 438 difftest.coreid := io.hartId 439 difftest.valid := io.out.fire && 440 (uop.fuOpType === LSUOpType.sc_d || uop.fuOpType === LSUOpType.sc_w) 441 difftest.success := is_lrsc_valid 442 } 443} 444