1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIOWithVaddr, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 26import difftest._ 27import xiangshan.ExceptionNO._ 28import xiangshan.backend.fu.PMPRespBundle 29 30class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 31 val io = IO(new Bundle() { 32 val hartId = Input(UInt(8.W)) 33 val in = Flipped(Decoupled(new ExuInput)) 34 val storeDataIn = Flipped(Valid(new ExuOutput)) // src2 from rs 35 val out = Decoupled(new ExuOutput) 36 val dcache = new DCacheWordIOWithVaddr 37 val dtlb = new TlbRequestIO 38 val pmpResp = Flipped(new PMPRespBundle()) 39 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 40 val flush_sbuffer = new SbufferFlushBundle 41 val feedbackSlow = ValidIO(new RSFeedback) 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 44 val csrCtrl = Flipped(new CustomCSRCtrlIO) 45 }) 46 47 //------------------------------------------------------- 48 // Atomics Memory Accsess FSM 49 //------------------------------------------------------- 50 val s_invalid :: s_tlb :: s_pm :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(8) 51 val state = RegInit(s_invalid) 52 val data_valid = RegInit(false.B) 53 val in = Reg(new ExuInput()) 54 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 55 val atom_override_xtval = RegInit(false.B) 56 // paddr after translation 57 val paddr = Reg(UInt()) 58 val is_mmio = Reg(Bool()) 59 // pmp check 60 val static_pm = Reg(Valid(Bool())) // valid for static, bits for mmio 61 // dcache response data 62 val resp_data = Reg(UInt()) 63 val resp_data_wire = WireInit(0.U) 64 val is_lrsc_valid = Reg(Bool()) 65 66 // Difftest signals 67 val paddr_reg = Reg(UInt(64.W)) 68 val data_reg = Reg(UInt(64.W)) 69 val mask_reg = Reg(UInt(8.W)) 70 val fuop_reg = Reg(UInt(8.W)) 71 72 io.exceptionAddr.valid := atom_override_xtval 73 io.exceptionAddr.bits := in.src(0) 74 75 // assign default value to output signals 76 io.in.ready := false.B 77 io.out.valid := false.B 78 io.out.bits := DontCare 79 80 io.dcache.req.valid := false.B 81 io.dcache.req.bits := DontCare 82 io.dcache.resp.ready := false.B 83 84 io.dtlb.req.valid := false.B 85 io.dtlb.req.bits := DontCare 86 io.dtlb.resp.ready := false.B 87 88 io.flush_sbuffer.valid := false.B 89 90 XSDebug("state: %d\n", state) 91 92 when (state === s_invalid) { 93 io.in.ready := true.B 94 when (io.in.fire()) { 95 in := io.in.bits 96 in.src(1) := in.src(1) // leave src2 unchanged 97 state := s_tlb 98 } 99 } 100 101 when (io.storeDataIn.fire()) { 102 in.src(1) := io.storeDataIn.bits.data 103 data_valid := true.B 104 } 105 106 assert(!(io.storeDataIn.fire() && data_valid), "atomic unit re-receive data") 107 108 // Send TLB feedback to store issue queue 109 // we send feedback right after we receives request 110 // also, we always treat amo as tlb hit 111 // since we will continue polling tlb all by ourself 112 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 113 io.feedbackSlow.bits.hit := true.B 114 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 115 io.feedbackSlow.bits.flushState := DontCare 116 io.feedbackSlow.bits.sourceType := DontCare 117 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 118 119 // tlb translation, manipulating signals && deal with exception 120 when (state === s_tlb) { 121 // send req to dtlb 122 // keep firing until tlb hit 123 io.dtlb.req.valid := true.B 124 io.dtlb.req.bits.vaddr := in.src(0) 125 io.dtlb.req.bits.robIdx := in.uop.robIdx 126 io.dtlb.resp.ready := true.B 127 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 128 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 129 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 130 io.dtlb.req.bits.debug.isFirstIssue := false.B 131 132 when(io.dtlb.resp.fire){ 133 paddr := io.dtlb.resp.bits.paddr 134 // exception handling 135 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 136 "b00".U -> true.B, //b 137 "b01".U -> (in.src(0)(0) === 0.U), //h 138 "b10".U -> (in.src(0)(1,0) === 0.U), //w 139 "b11".U -> (in.src(0)(2,0) === 0.U) //d 140 )) 141 exceptionVec(storeAddrMisaligned) := !addrAligned 142 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 143 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 144 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 145 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 146 static_pm := io.dtlb.resp.bits.static_pm 147 148 when (!io.dtlb.resp.bits.miss) { 149 when (!addrAligned) { 150 // NOTE: when addrAligned, do not need to wait tlb actually 151 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 152 // if there are exceptions, no need to execute it 153 state := s_finish 154 atom_override_xtval := true.B 155 } .otherwise { 156 state := s_pm 157 } 158 } 159 } 160 } 161 162 when (state === s_pm) { 163 val pmp = WireInit(io.pmpResp) 164 when (static_pm.valid) { 165 pmp.ld := false.B 166 pmp.st := false.B 167 pmp.instr := false.B 168 pmp.mmio := static_pm.bits 169 } 170 is_mmio := pmp.mmio 171 // NOTE: only handle load/store exception here, if other exception happens, don't send here 172 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 173 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 174 val exception_pa = pmp.st 175 when (exception_va || exception_pa) { 176 state := s_finish 177 atom_override_xtval := true.B 178 }.otherwise { 179 state := s_flush_sbuffer_req 180 } 181 } 182 183 when (state === s_flush_sbuffer_req) { 184 io.flush_sbuffer.valid := true.B 185 state := s_flush_sbuffer_resp 186 } 187 188 when (state === s_flush_sbuffer_resp) { 189 when (io.flush_sbuffer.empty) { 190 state := s_cache_req 191 } 192 } 193 194 when (state === s_cache_req) { 195 io.dcache.req.valid := true.B 196 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 197 LSUOpType.lr_w -> M_XLR, 198 LSUOpType.sc_w -> M_XSC, 199 LSUOpType.amoswap_w -> M_XA_SWAP, 200 LSUOpType.amoadd_w -> M_XA_ADD, 201 LSUOpType.amoxor_w -> M_XA_XOR, 202 LSUOpType.amoand_w -> M_XA_AND, 203 LSUOpType.amoor_w -> M_XA_OR, 204 LSUOpType.amomin_w -> M_XA_MIN, 205 LSUOpType.amomax_w -> M_XA_MAX, 206 LSUOpType.amominu_w -> M_XA_MINU, 207 LSUOpType.amomaxu_w -> M_XA_MAXU, 208 209 LSUOpType.lr_d -> M_XLR, 210 LSUOpType.sc_d -> M_XSC, 211 LSUOpType.amoswap_d -> M_XA_SWAP, 212 LSUOpType.amoadd_d -> M_XA_ADD, 213 LSUOpType.amoxor_d -> M_XA_XOR, 214 LSUOpType.amoand_d -> M_XA_AND, 215 LSUOpType.amoor_d -> M_XA_OR, 216 LSUOpType.amomin_d -> M_XA_MIN, 217 LSUOpType.amomax_d -> M_XA_MAX, 218 LSUOpType.amominu_d -> M_XA_MINU, 219 LSUOpType.amomaxu_d -> M_XA_MAXU 220 )) 221 222 io.dcache.req.bits.addr := paddr 223 io.dcache.req.bits.vaddr := in.src(0) // vaddr 224 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 225 // TODO: atomics do need mask: fix mask 226 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 227 io.dcache.req.bits.id := DontCare 228 229 when(io.dcache.req.fire()){ 230 state := s_cache_resp 231 paddr_reg := io.dcache.req.bits.addr 232 data_reg := io.dcache.req.bits.data 233 mask_reg := io.dcache.req.bits.mask 234 fuop_reg := in.uop.ctrl.fuOpType 235 } 236 } 237 238 when (state === s_cache_resp) { 239 io.dcache.resp.ready := data_valid 240 when(io.dcache.resp.fire()) { 241 is_lrsc_valid := io.dcache.resp.bits.id 242 val rdata = io.dcache.resp.bits.data 243 val rdataSel = LookupTree(paddr(2, 0), List( 244 "b000".U -> rdata(63, 0), 245 "b001".U -> rdata(63, 8), 246 "b010".U -> rdata(63, 16), 247 "b011".U -> rdata(63, 24), 248 "b100".U -> rdata(63, 32), 249 "b101".U -> rdata(63, 40), 250 "b110".U -> rdata(63, 48), 251 "b111".U -> rdata(63, 56) 252 )) 253 254 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 255 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 256 LSUOpType.sc_w -> rdata, 257 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 258 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 259 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 260 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 261 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 262 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 263 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 264 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 265 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 266 267 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 268 LSUOpType.sc_d -> rdata, 269 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 270 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 271 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 272 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 273 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 274 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 275 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 276 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 277 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 278 )) 279 280 when (io.dcache.resp.bits.error && io.csrCtrl.cache_error_enable) { 281 val isLr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 282 exceptionVec(loadAccessFault) := isLr 283 exceptionVec(storeAccessFault) := !isLr 284 assert(!exceptionVec(loadAccessFault)) 285 assert(!exceptionVec(storeAccessFault)) 286 } 287 288 resp_data := resp_data_wire 289 state := s_finish 290 } 291 } 292 293 when (state === s_finish) { 294 io.out.valid := true.B 295 io.out.bits.uop := in.uop 296 io.out.bits.uop.cf.exceptionVec := exceptionVec 297 io.out.bits.data := resp_data 298 io.out.bits.redirectValid := false.B 299 io.out.bits.redirect := DontCare 300 io.out.bits.debug.isMMIO := is_mmio 301 io.out.bits.debug.paddr := paddr 302 when (io.out.fire()) { 303 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 304 state := s_invalid 305 } 306 data_valid := false.B 307 } 308 309 when (io.redirect.valid) { 310 atom_override_xtval := false.B 311 } 312 313 if (env.EnableDifftest) { 314 val difftest = Module(new DifftestAtomicEvent) 315 difftest.io.clock := clock 316 difftest.io.coreid := io.hartId 317 difftest.io.atomicResp := io.dcache.resp.fire() 318 difftest.io.atomicAddr := paddr_reg 319 difftest.io.atomicData := data_reg 320 difftest.io.atomicMask := mask_reg 321 difftest.io.atomicFuop := fuop_reg 322 difftest.io.atomicOut := resp_data_wire 323 } 324 325 if (env.EnableDifftest || env.AlwaysBasicDiff) { 326 val uop = io.out.bits.uop 327 val difftest = Module(new DifftestLrScEvent) 328 difftest.io.clock := clock 329 difftest.io.coreid := io.hartId 330 difftest.io.valid := io.out.fire && 331 (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w) 332 difftest.io.success := is_lrsc_valid 333 } 334} 335