1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIOWithVaddr, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 26import difftest._ 27import xiangshan.ExceptionNO._ 28import xiangshan.backend.fu.PMPRespBundle 29 30class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 31 val io = IO(new Bundle() { 32 val hartId = Input(UInt(8.W)) 33 val in = Flipped(Decoupled(new ExuInput)) 34 val storeDataIn = Flipped(Valid(new ExuOutput)) // src2 from rs 35 val out = Decoupled(new ExuOutput) 36 val dcache = new DCacheWordIOWithVaddr 37 val dtlb = new TlbRequestIO 38 val pmpResp = Flipped(new PMPRespBundle()) 39 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 40 val flush_sbuffer = new SbufferFlushBundle 41 val feedbackSlow = ValidIO(new RSFeedback) 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 44 val csrCtrl = Flipped(new CustomCSRCtrlIO) 45 }) 46 47 //------------------------------------------------------- 48 // Atomics Memory Accsess FSM 49 //------------------------------------------------------- 50 val s_invalid :: s_tlb :: s_pm :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(8) 51 val state = RegInit(s_invalid) 52 val data_valid = RegInit(false.B) 53 val in = Reg(new ExuInput()) 54 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 55 val atom_override_xtval = RegInit(false.B) 56 // paddr after translation 57 val paddr = Reg(UInt()) 58 val is_mmio = Reg(Bool()) 59 // dcache response data 60 val resp_data = Reg(UInt()) 61 val resp_data_wire = WireInit(0.U) 62 val is_lrsc_valid = Reg(Bool()) 63 64 // Difftest signals 65 val paddr_reg = Reg(UInt(64.W)) 66 val data_reg = Reg(UInt(64.W)) 67 val mask_reg = Reg(UInt(8.W)) 68 val fuop_reg = Reg(UInt(8.W)) 69 70 io.exceptionAddr.valid := atom_override_xtval 71 io.exceptionAddr.bits := in.src(0) 72 73 // assign default value to output signals 74 io.in.ready := false.B 75 io.out.valid := false.B 76 io.out.bits := DontCare 77 78 io.dcache.req.valid := false.B 79 io.dcache.req.bits := DontCare 80 io.dcache.resp.ready := false.B 81 82 io.dtlb.req.valid := false.B 83 io.dtlb.req.bits := DontCare 84 io.dtlb.resp.ready := false.B 85 86 io.flush_sbuffer.valid := false.B 87 88 XSDebug("state: %d\n", state) 89 90 when (state === s_invalid) { 91 io.in.ready := true.B 92 when (io.in.fire()) { 93 in := io.in.bits 94 in.src(1) := in.src(1) // leave src2 unchanged 95 state := s_tlb 96 } 97 } 98 99 when (io.storeDataIn.fire()) { 100 in.src(1) := io.storeDataIn.bits.data 101 data_valid := true.B 102 } 103 104 assert(!(io.storeDataIn.fire() && data_valid), "atomic unit re-receive data") 105 106 // Send TLB feedback to store issue queue 107 // we send feedback right after we receives request 108 // also, we always treat amo as tlb hit 109 // since we will continue polling tlb all by ourself 110 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 111 io.feedbackSlow.bits.hit := true.B 112 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 113 io.feedbackSlow.bits.flushState := DontCare 114 io.feedbackSlow.bits.sourceType := DontCare 115 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 116 117 // tlb translation, manipulating signals && deal with exception 118 when (state === s_tlb) { 119 // send req to dtlb 120 // keep firing until tlb hit 121 io.dtlb.req.valid := true.B 122 io.dtlb.req.bits.vaddr := in.src(0) 123 io.dtlb.req.bits.robIdx := in.uop.robIdx 124 io.dtlb.resp.ready := true.B 125 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 126 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 127 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 128 io.dtlb.req.bits.debug.isFirstIssue := false.B 129 130 when(io.dtlb.resp.fire){ 131 paddr := io.dtlb.resp.bits.paddr 132 // exception handling 133 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 134 "b00".U -> true.B, //b 135 "b01".U -> (in.src(0)(0) === 0.U), //h 136 "b10".U -> (in.src(0)(1,0) === 0.U), //w 137 "b11".U -> (in.src(0)(2,0) === 0.U) //d 138 )) 139 exceptionVec(storeAddrMisaligned) := !addrAligned 140 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 141 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 142 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 143 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 144 145 when (!io.dtlb.resp.bits.miss) { 146 when (!addrAligned) { 147 // NOTE: when addrAligned, do not need to wait tlb actually 148 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 149 // if there are exceptions, no need to execute it 150 state := s_finish 151 atom_override_xtval := true.B 152 } .otherwise { 153 state := s_pm 154 } 155 } 156 } 157 } 158 159 when (state === s_pm) { 160 is_mmio := io.pmpResp.mmio 161 // NOTE: only handle load/store exception here, if other exception happens, don't send here 162 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 163 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 164 val exception_pa = io.pmpResp.st 165 when (exception_va || exception_pa) { 166 state := s_finish 167 atom_override_xtval := true.B 168 }.otherwise { 169 state := s_flush_sbuffer_req 170 } 171 } 172 173 when (state === s_flush_sbuffer_req) { 174 io.flush_sbuffer.valid := true.B 175 state := s_flush_sbuffer_resp 176 } 177 178 when (state === s_flush_sbuffer_resp) { 179 when (io.flush_sbuffer.empty) { 180 state := s_cache_req 181 } 182 } 183 184 when (state === s_cache_req) { 185 io.dcache.req.valid := true.B 186 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 187 LSUOpType.lr_w -> M_XLR, 188 LSUOpType.sc_w -> M_XSC, 189 LSUOpType.amoswap_w -> M_XA_SWAP, 190 LSUOpType.amoadd_w -> M_XA_ADD, 191 LSUOpType.amoxor_w -> M_XA_XOR, 192 LSUOpType.amoand_w -> M_XA_AND, 193 LSUOpType.amoor_w -> M_XA_OR, 194 LSUOpType.amomin_w -> M_XA_MIN, 195 LSUOpType.amomax_w -> M_XA_MAX, 196 LSUOpType.amominu_w -> M_XA_MINU, 197 LSUOpType.amomaxu_w -> M_XA_MAXU, 198 199 LSUOpType.lr_d -> M_XLR, 200 LSUOpType.sc_d -> M_XSC, 201 LSUOpType.amoswap_d -> M_XA_SWAP, 202 LSUOpType.amoadd_d -> M_XA_ADD, 203 LSUOpType.amoxor_d -> M_XA_XOR, 204 LSUOpType.amoand_d -> M_XA_AND, 205 LSUOpType.amoor_d -> M_XA_OR, 206 LSUOpType.amomin_d -> M_XA_MIN, 207 LSUOpType.amomax_d -> M_XA_MAX, 208 LSUOpType.amominu_d -> M_XA_MINU, 209 LSUOpType.amomaxu_d -> M_XA_MAXU 210 )) 211 212 io.dcache.req.bits.addr := paddr 213 io.dcache.req.bits.vaddr := in.src(0) // vaddr 214 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 215 // TODO: atomics do need mask: fix mask 216 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 217 io.dcache.req.bits.id := DontCare 218 219 when(io.dcache.req.fire()){ 220 state := s_cache_resp 221 paddr_reg := io.dcache.req.bits.addr 222 data_reg := io.dcache.req.bits.data 223 mask_reg := io.dcache.req.bits.mask 224 fuop_reg := in.uop.ctrl.fuOpType 225 } 226 } 227 228 when (state === s_cache_resp) { 229 io.dcache.resp.ready := data_valid 230 when(io.dcache.resp.fire()) { 231 is_lrsc_valid := io.dcache.resp.bits.id 232 val rdata = io.dcache.resp.bits.data 233 val rdataSel = LookupTree(paddr(2, 0), List( 234 "b000".U -> rdata(63, 0), 235 "b001".U -> rdata(63, 8), 236 "b010".U -> rdata(63, 16), 237 "b011".U -> rdata(63, 24), 238 "b100".U -> rdata(63, 32), 239 "b101".U -> rdata(63, 40), 240 "b110".U -> rdata(63, 48), 241 "b111".U -> rdata(63, 56) 242 )) 243 244 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 245 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 246 LSUOpType.sc_w -> rdata, 247 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 248 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 249 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 250 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 251 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 252 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 253 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 254 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 255 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 256 257 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 258 LSUOpType.sc_d -> rdata, 259 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 260 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 261 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 262 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 263 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 264 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 265 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 266 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 267 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 268 )) 269 270 when (io.dcache.resp.bits.error && io.csrCtrl.cache_error_enable) { 271 val isLr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 272 exceptionVec(loadAccessFault) := isLr 273 exceptionVec(storeAccessFault) := !isLr 274 assert(!exceptionVec(loadAccessFault)) 275 assert(!exceptionVec(storeAccessFault)) 276 } 277 278 resp_data := resp_data_wire 279 state := s_finish 280 } 281 } 282 283 when (state === s_finish) { 284 io.out.valid := true.B 285 io.out.bits.uop := in.uop 286 io.out.bits.uop.cf.exceptionVec := exceptionVec 287 io.out.bits.data := resp_data 288 io.out.bits.redirectValid := false.B 289 io.out.bits.redirect := DontCare 290 io.out.bits.debug.isMMIO := is_mmio 291 io.out.bits.debug.paddr := paddr 292 when (io.out.fire()) { 293 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 294 state := s_invalid 295 } 296 data_valid := false.B 297 } 298 299 when (io.redirect.valid) { 300 atom_override_xtval := false.B 301 } 302 303 if (env.EnableDifftest) { 304 val difftest = Module(new DifftestAtomicEvent) 305 difftest.io.clock := clock 306 difftest.io.coreid := io.hartId 307 difftest.io.atomicResp := io.dcache.resp.fire() 308 difftest.io.atomicAddr := paddr_reg 309 difftest.io.atomicData := data_reg 310 difftest.io.atomicMask := mask_reg 311 difftest.io.atomicFuop := fuop_reg 312 difftest.io.atomicOut := resp_data_wire 313 } 314 315 if (env.EnableDifftest || env.AlwaysBasicDiff) { 316 val uop = io.out.bits.uop 317 val difftest = Module(new DifftestLrScEvent) 318 difftest.io.clock := clock 319 difftest.io.coreid := io.hartId 320 difftest.io.valid := io.out.fire && 321 (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w) 322 difftest.io.success := is_lrsc_valid 323 } 324} 325