1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class AtomicsUnit extends XSModule with MemoryOpConstants{ 11 val io = IO(new Bundle() { 12 val in = Flipped(Decoupled(new ExuInput)) 13 val out = Decoupled(new ExuOutput) 14 val dcache = new DCacheWordIO 15 val dtlb = new TlbRequestIO 16 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 17 val flush_sbuffer = new SbufferFlushBundle 18 val tlbFeedback = ValidIO(new TlbFeedback) 19 val redirect = Flipped(ValidIO(new Redirect)) 20 val flush = Input(Bool()) 21 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 22 }) 23 24 val difftestIO = IO(new Bundle() { 25 val atomicResp = Output(Bool()) 26 val atomicAddr = Output(UInt(64.W)) 27 val atomicData = Output(UInt(64.W)) 28 val atomicMask = Output(UInt(8.W)) 29 val atomicFuop = Output(UInt(8.W)) 30 val atomicOut = Output(UInt(64.W)) 31 }) 32 difftestIO <> DontCare 33 34 //------------------------------------------------------- 35 // Atomics Memory Accsess FSM 36 //------------------------------------------------------- 37 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 38 val state = RegInit(s_invalid) 39 val in = Reg(new ExuInput()) 40 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 41 val atom_override_xtval = RegInit(false.B) 42 // paddr after translation 43 val paddr = Reg(UInt()) 44 val is_mmio = Reg(Bool()) 45 // dcache response data 46 val resp_data = Reg(UInt()) 47 val resp_data_wire = WireInit(0.U) 48 val is_lrsc_valid = Reg(Bool()) 49 50 // Difftest signals 51 val paddr_reg = Reg(UInt(64.W)) 52 val data_reg = Reg(UInt(64.W)) 53 val mask_reg = Reg(UInt(8.W)) 54 val fuop_reg = Reg(UInt(8.W)) 55 56 io.exceptionAddr.valid := atom_override_xtval 57 io.exceptionAddr.bits := in.src1 58 59 // assign default value to output signals 60 io.in.ready := false.B 61 io.out.valid := false.B 62 io.out.bits := DontCare 63 64 io.dcache.req.valid := false.B 65 io.dcache.req.bits := DontCare 66 io.dcache.resp.ready := false.B 67 68 io.dtlb.req.valid := false.B 69 io.dtlb.req.bits := DontCare 70 io.dtlb.resp.ready := false.B 71 72 io.flush_sbuffer.valid := false.B 73 74 XSDebug("state: %d\n", state) 75 76 when (state === s_invalid) { 77 io.in.ready := true.B 78 when (io.in.fire()) { 79 in := io.in.bits 80 state := s_tlb 81 } 82 } 83 84 // Send TLB feedback to store issue queue 85 // we send feedback right after we receives request 86 // also, we always treat amo as tlb hit 87 // since we will continue polling tlb all by ourself 88 io.tlbFeedback.valid := RegNext(RegNext(io.in.valid)) 89 io.tlbFeedback.bits.hit := true.B 90 io.tlbFeedback.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 91 io.tlbFeedback.bits.flushState := DontCare 92 93 // tlb translation, manipulating signals && deal with exception 94 when (state === s_tlb) { 95 // send req to dtlb 96 // keep firing until tlb hit 97 io.dtlb.req.valid := true.B 98 io.dtlb.req.bits.vaddr := in.src1 99 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 100 io.dtlb.resp.ready := true.B 101 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 102 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 103 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 104 105 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 106 // exception handling 107 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 108 "b00".U -> true.B, //b 109 "b01".U -> (in.src1(0) === 0.U), //h 110 "b10".U -> (in.src1(1,0) === 0.U), //w 111 "b11".U -> (in.src1(2,0) === 0.U) //d 112 )) 113 exceptionVec(storeAddrMisaligned) := !addrAligned 114 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 115 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 116 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 117 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 118 val exception = !addrAligned || 119 io.dtlb.resp.bits.excp.pf.st || 120 io.dtlb.resp.bits.excp.pf.ld || 121 io.dtlb.resp.bits.excp.af.st || 122 io.dtlb.resp.bits.excp.af.ld 123 is_mmio := io.dtlb.resp.bits.mmio 124 when (exception) { 125 // check for exceptions 126 // if there are exceptions, no need to execute it 127 state := s_finish 128 atom_override_xtval := true.B 129 } .otherwise { 130 paddr := io.dtlb.resp.bits.paddr 131 state := s_flush_sbuffer_req 132 } 133 } 134 } 135 136 137 when (state === s_flush_sbuffer_req) { 138 io.flush_sbuffer.valid := true.B 139 state := s_flush_sbuffer_resp 140 } 141 142 when (state === s_flush_sbuffer_resp) { 143 when (io.flush_sbuffer.empty) { 144 state := s_cache_req 145 } 146 } 147 148 when (state === s_cache_req) { 149 io.dcache.req.valid := true.B 150 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 151 LSUOpType.lr_w -> M_XLR, 152 LSUOpType.sc_w -> M_XSC, 153 LSUOpType.amoswap_w -> M_XA_SWAP, 154 LSUOpType.amoadd_w -> M_XA_ADD, 155 LSUOpType.amoxor_w -> M_XA_XOR, 156 LSUOpType.amoand_w -> M_XA_AND, 157 LSUOpType.amoor_w -> M_XA_OR, 158 LSUOpType.amomin_w -> M_XA_MIN, 159 LSUOpType.amomax_w -> M_XA_MAX, 160 LSUOpType.amominu_w -> M_XA_MINU, 161 LSUOpType.amomaxu_w -> M_XA_MAXU, 162 163 LSUOpType.lr_d -> M_XLR, 164 LSUOpType.sc_d -> M_XSC, 165 LSUOpType.amoswap_d -> M_XA_SWAP, 166 LSUOpType.amoadd_d -> M_XA_ADD, 167 LSUOpType.amoxor_d -> M_XA_XOR, 168 LSUOpType.amoand_d -> M_XA_AND, 169 LSUOpType.amoor_d -> M_XA_OR, 170 LSUOpType.amomin_d -> M_XA_MIN, 171 LSUOpType.amomax_d -> M_XA_MAX, 172 LSUOpType.amominu_d -> M_XA_MINU, 173 LSUOpType.amomaxu_d -> M_XA_MAXU 174 )) 175 176 io.dcache.req.bits.addr := paddr 177 io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0)) 178 // TODO: atomics do need mask: fix mask 179 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 180 io.dcache.req.bits.id := DontCare 181 182 when(io.dcache.req.fire()){ 183 state := s_cache_resp 184 paddr_reg := io.dcache.req.bits.addr 185 data_reg := io.dcache.req.bits.data 186 mask_reg := io.dcache.req.bits.mask 187 fuop_reg := in.uop.ctrl.fuOpType 188 } 189 } 190 191 when (state === s_cache_resp) { 192 io.dcache.resp.ready := true.B 193 when(io.dcache.resp.fire()) { 194 is_lrsc_valid := io.dcache.resp.bits.id 195 val rdata = io.dcache.resp.bits.data 196 val rdataSel = LookupTree(paddr(2, 0), List( 197 "b000".U -> rdata(63, 0), 198 "b001".U -> rdata(63, 8), 199 "b010".U -> rdata(63, 16), 200 "b011".U -> rdata(63, 24), 201 "b100".U -> rdata(63, 32), 202 "b101".U -> rdata(63, 40), 203 "b110".U -> rdata(63, 48), 204 "b111".U -> rdata(63, 56) 205 )) 206 207 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 208 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 209 LSUOpType.sc_w -> rdata, 210 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 211 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 212 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 213 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 214 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 215 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 216 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 217 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 218 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 219 220 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 221 LSUOpType.sc_d -> rdata, 222 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 223 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 224 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 225 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 226 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 227 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 228 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 229 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 230 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 231 )) 232 233 resp_data := resp_data_wire 234 state := s_finish 235 } 236 } 237 238 when (state === s_finish) { 239 io.out.valid := true.B 240 io.out.bits.uop := in.uop 241 io.out.bits.uop.cf.exceptionVec := exceptionVec 242 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 243 io.out.bits.data := resp_data 244 io.out.bits.redirectValid := false.B 245 io.out.bits.redirect := DontCare 246 io.out.bits.debug.isMMIO := is_mmio 247 io.out.bits.debug.paddr := paddr 248 when (io.out.fire()) { 249 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 250 state := s_invalid 251 } 252 } 253 254 when(io.redirect.valid || io.flush){ 255 atom_override_xtval := false.B 256 } 257 258 if (!env.FPGAPlatform) { 259 difftestIO.atomicResp := WireInit(io.dcache.resp.fire()) 260 difftestIO.atomicAddr := WireInit(paddr_reg) 261 difftestIO.atomicData := WireInit(data_reg) 262 difftestIO.atomicMask := WireInit(mask_reg) 263 difftestIO.atomicFuop := WireInit(fuop_reg) 264 difftestIO.atomicOut := resp_data_wire 265 } 266} 267