1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.ExceptionNO._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.fu.NewCSR._ 31import xiangshan.backend.rob.RobPtr 32import xiangshan.backend.fu._ 33import xiangshan.backend.fu.util.SdtrigExt 34import xiangshan.mem.mdp._ 35import xiangshan.mem.Bundles._ 36import xiangshan.cache._ 37import xiangshan.cache.wpu.ReplayCarry 38import xiangshan.cache.mmu.{TlbCmd, TlbHintReq, TlbReq, TlbRequestIO, TlbResp} 39 40class HybridUnit(implicit p: Parameters) extends XSModule 41 with HasLoadHelper 42 with HasPerfEvents 43 with HasDCacheParameters 44 with HasCircularQueuePtrHelper 45 with HasVLSUParameters 46 with SdtrigExt 47{ 48 val io = IO(new Bundle() { 49 // control 50 val redirect = Flipped(ValidIO(new Redirect)) 51 val csrCtrl = Flipped(new CustomCSRCtrlIO) 52 53 // flow in 54 val lsin = Flipped(Decoupled(new MemExuInput)) 55 56 // flow out 57 val ldout = DecoupledIO(new MemExuOutput) 58 val stout = DecoupledIO(new MemExuOutput) 59 60 val ldu_io = new Bundle() { 61 // dcache 62 val dcache = new DCacheLoadIO 63 64 // data path 65 val sbuffer = new LoadForwardQueryIO 66 val ubuffer = new LoadForwardQueryIO 67 val vec_forward = new LoadForwardQueryIO 68 val lsq = new LoadToLsqIO 69 val tl_d_channel = Input(new DcacheToLduForwardIO) 70 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 71 val tlb_hint = Flipped(new TlbHintReq) 72 val l2_hint = Input(Valid(new L2ToL1Hint)) 73 74 // fast wakeup 75 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 76 77 // trigger 78 val trigger = Vec(TriggerNum, new LoadUnitTriggerIO) 79 80 // load to load fast path 81 val l2l_fwd_in = Input(new LoadToLoadIO) 82 val l2l_fwd_out = Output(new LoadToLoadIO) 83 84 val ld_fast_match = Input(Bool()) 85 val ld_fast_fuOpType = Input(UInt()) 86 val ld_fast_imm = Input(UInt(12.W)) 87 88 // hardware prefetch to l1 cache req 89 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) 90 91 // iq cancel 92 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 93 94 // iq wakeup, use to wakeup consumer uop at load s2 95 val wakeup = ValidIO(new DynInst) 96 97 // load ecc error 98 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 99 100 // schedule error query 101 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryBundle))) 102 103 // queue-based replay 104 val replay = Flipped(Decoupled(new LsPipelineBundle)) 105 val lq_rep_full = Input(Bool()) 106 107 // misc 108 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 109 110 // Load fast replay path 111 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 112 val fast_rep_out = Decoupled(new LqWriteBundle) 113 114 // Load RAR rollback 115 val rollback = Valid(new Redirect) 116 117 // perf 118 val debug_ls = Output(new DebugLsInfoBundle) 119 val lsTopdownInfo = Output(new LsTopdownInfo) 120 } 121 122 val stu_io = new Bundle() { 123 val dcache = new DCacheStoreIO 124 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 125 val issue = Valid(new MemExuInput) 126 val lsq = ValidIO(new LsPipelineBundle) 127 val lsq_replenish = Output(new LsPipelineBundle()) 128 val stld_nuke_query = Valid(new StoreNukeQueryBundle) 129 val st_mask_out = Valid(new StoreMaskBundle) 130 val debug_ls = Output(new DebugLsInfoBundle) 131 } 132 133 val vec_stu_io = new Bundle() { 134 val in = Flipped(DecoupledIO(new VecPipeBundle())) 135 val isFirstIssue = Input(Bool()) 136 val lsq = ValidIO(new LsPipelineBundle()) 137 val feedbackSlow = ValidIO(new VSFQFeedback) 138 } 139 140 // speculative for gated control 141 val s0_prefetch_spec = Output(Bool()) 142 val s1_prefetch_spec = Output(Bool()) 143 // prefetch 144 val prefetch_train = ValidIO(new LsPrefetchTrainBundle()) // provide prefetch info to sms 145 val prefetch_train_l1 = ValidIO(new LsPrefetchTrainBundle()) // provide prefetch info to stream & stride 146 val canAcceptLowConfPrefetch = Output(Bool()) 147 val canAcceptHighConfPrefetch = Output(Bool()) 148 val correctMissTrain = Input(Bool()) 149 150 // data path 151 val tlb = new TlbRequestIO(2) 152 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 153 154 // rs feedback 155 val feedback_fast = ValidIO(new RSFeedback) // stage 2 156 val feedback_slow = ValidIO(new RSFeedback) // stage 3 157 158 // for store trigger 159 val fromCsrTrigger = Input(new CsrTriggerBundle) 160 }) 161 162 PerfCCT.updateInstPos(io.lsin.bits.uop.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.lsin.valid, clock, reset) 163 164 val StorePrefetchL1Enabled = EnableStorePrefetchAtCommit || EnableStorePrefetchAtIssue || EnableStorePrefetchSPB 165 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) 166 167 // Pipeline 168 // -------------------------------------------------------------------------------- 169 // stage 0 170 // -------------------------------------------------------------------------------- 171 // generate addr, use addr to query DCache and DTLB 172 val s0_valid = Wire(Bool()) 173 val s0_dcache_ready = Wire(Bool()) 174 val s0_kill = Wire(Bool()) 175 val s0_vaddr = Wire(UInt(VAddrBits.W)) 176 val s0_mask = Wire(UInt((VLEN/8).W)) 177 val s0_uop = Wire(new DynInst) 178 val s0_has_rob_entry = Wire(Bool()) 179 val s0_mshrid = Wire(UInt()) 180 val s0_try_l2l = Wire(Bool()) 181 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 182 val s0_isFirstIssue = Wire(Bool()) 183 val s0_fast_rep = Wire(Bool()) 184 val s0_ld_rep = Wire(Bool()) 185 val s0_l2l_fwd = Wire(Bool()) 186 val s0_sched_idx = Wire(UInt()) 187 val s0_can_go = s1_ready 188 val s0_fire = s0_valid && s0_dcache_ready && s0_can_go 189 val s0_out = Wire(new LqWriteBundle) 190 // vector 191 val s0_isvec = WireInit(false.B) 192 val s0_vecActive = WireInit(true.B) 193 // val s0_flowPtr = WireInit(0.U.asTypeOf(new VsFlowPtr)) 194 val s0_isLastElem = WireInit(false.B) 195 196 // load flow select/gen 197 // src0: super load replayed by LSQ (cache miss replay) (io.ldu_io.replay) 198 // src1: fast load replay (io.ldu_io.fast_rep_in) 199 // src2: load replayed by LSQ (io.ldu_io.replay) 200 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 201 // src4: int read / software prefetch first issue from RS (io.in) 202 // src5: vec read first issue from RS (TODO) 203 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 204 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 205 // priority: high to low 206 val s0_ld_flow = FuType.isLoad(s0_uop.fuType) || FuType.isVLoad(s0_uop.fuType) 207 val s0_rep_stall = io.lsin.valid && isAfter(io.ldu_io.replay.bits.uop.robIdx, io.lsin.bits.uop.robIdx) 208 private val SRC_NUM = 8 209 private val Seq( 210 super_rep_idx, fast_rep_idx, lsq_rep_idx, high_pf_idx, 211 int_iss_idx, vec_iss_idx, l2l_fwd_idx, low_pf_idx 212 ) = (0 until SRC_NUM).toSeq 213 // load flow source valid 214 val s0_src_valid_vec = WireInit(VecInit(Seq( 215 io.ldu_io.replay.valid && io.ldu_io.replay.bits.forward_tlDchannel, 216 io.ldu_io.fast_rep_in.valid, 217 io.ldu_io.replay.valid && !io.ldu_io.replay.bits.forward_tlDchannel && !s0_rep_stall, 218 io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence > 0.U, 219 io.lsin.valid, // int flow first issue or software prefetch 220 io.vec_stu_io.in.valid, 221 io.ldu_io.l2l_fwd_in.valid && io.ldu_io.ld_fast_match, 222 io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence === 0.U, 223 ))) 224 // load flow source ready 225 val s0_src_ready_vec = Wire(Vec(SRC_NUM, Bool())) 226 s0_src_ready_vec(0) := true.B 227 for(i <- 1 until SRC_NUM){ 228 s0_src_ready_vec(i) := !s0_src_valid_vec.take(i).reduce(_ || _) 229 } 230 // load flow source select (OH) 231 val s0_src_select_vec = WireInit(VecInit((0 until SRC_NUM).map{i => s0_src_valid_vec(i) && s0_src_ready_vec(i)})) 232 val s0_hw_prf_select = s0_src_select_vec(high_pf_idx) || s0_src_select_vec(low_pf_idx) 233 234 if (backendParams.debugEn){ 235 dontTouch(s0_src_valid_vec) 236 dontTouch(s0_src_ready_vec) 237 dontTouch(s0_src_select_vec) 238 } 239 240 s0_valid := s0_src_valid_vec.reduce(_ || _) && !s0_kill 241 242 // which is S0's out is ready and dcache is ready 243 val s0_try_ptr_chasing = s0_src_select_vec(l2l_fwd_idx) 244 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.ldu_io.dcache.req.ready 245 val s0_ptr_chasing_vaddr = io.ldu_io.l2l_fwd_in.data(5, 0) +& io.ldu_io.ld_fast_imm(5, 0) 246 val s0_ptr_chasing_canceled = WireInit(false.B) 247 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 248 249 // prefetch related ctrl signal 250 val s0_prf = Wire(Bool()) 251 val s0_prf_rd = Wire(Bool()) 252 val s0_prf_wr = Wire(Bool()) 253 val s0_hw_prf = s0_hw_prf_select 254 255 io.canAcceptLowConfPrefetch := s0_src_ready_vec(low_pf_idx) && io.ldu_io.dcache.req.ready 256 io.canAcceptHighConfPrefetch := s0_src_ready_vec(high_pf_idx) && io.ldu_io.dcache.req.ready 257 258 if (StorePrefetchL1Enabled) { 259 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, io.stu_io.dcache.req.ready) 260 } else { 261 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, true.B) 262 } 263 264 // query DTLB 265 io.tlb.req.valid := s0_valid && s0_dcache_ready 266 io.tlb.req.bits.cmd := Mux(s0_prf, 267 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 268 Mux(s0_ld_flow, TlbCmd.read, TlbCmd.write) 269 ) 270 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.paddr, s0_vaddr) 271 io.tlb.req.bits.size := Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1, 0), LSUOpType.size(s0_uop.fuOpType)) // may broken if use it in feature 272 io.tlb.req.bits.kill := s0_kill 273 io.tlb.req.bits.memidx.is_ld := s0_ld_flow 274 io.tlb.req.bits.memidx.is_st := !s0_ld_flow 275 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 276 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 277 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 278 io.tlb.req.bits.debug.pc := s0_uop.pc 279 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 280 281 // query DCache 282 // for load 283 io.ldu_io.dcache.req.valid := s0_valid && s0_dcache_ready && s0_ld_flow 284 io.ldu_io.dcache.req.bits.cmd := Mux(s0_prf_rd, MemoryOpConstants.M_PFR, 285 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD)) 286 io.ldu_io.dcache.req.bits.vaddr := s0_vaddr 287 io.ldu_io.dcache.req.bits.mask := s0_mask 288 io.ldu_io.dcache.req.bits.data := DontCare 289 io.ldu_io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 290 io.ldu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 291 io.ldu_io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 292 io.ldu_io.dcache.req.bits.replayCarry := s0_rep_carry 293 io.ldu_io.dcache.req.bits.id := DontCare // TODO: update cache meta 294 io.ldu_io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 295 io.ldu_io.dcache.is128Req := is128Bit(io.vec_stu_io.in.bits.alignedType) && io.vec_stu_io.in.valid && s0_src_select_vec(vec_iss_idx) 296 297 // for store 298 io.stu_io.dcache.req.valid := s0_valid && s0_dcache_ready && !s0_ld_flow && !s0_prf 299 io.stu_io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 300 io.stu_io.dcache.req.bits.vaddr := s0_vaddr 301 io.stu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, STORE_SOURCE.U) 302 303 // load flow priority mux 304 def fromNullSource() = { 305 s0_vaddr := 0.U 306 s0_mask := 0.U 307 s0_uop := 0.U.asTypeOf(new DynInst) 308 s0_try_l2l := false.B 309 s0_has_rob_entry := false.B 310 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 311 s0_mshrid := 0.U 312 s0_isFirstIssue := false.B 313 s0_fast_rep := false.B 314 s0_ld_rep := false.B 315 s0_l2l_fwd := false.B 316 s0_prf := false.B 317 s0_prf_rd := false.B 318 s0_prf_wr := false.B 319 s0_sched_idx := 0.U 320 } 321 322 def fromFastReplaySource(src: LqWriteBundle) = { 323 s0_vaddr := src.vaddr 324 s0_mask := src.mask 325 s0_uop := src.uop 326 s0_try_l2l := false.B 327 s0_has_rob_entry := src.hasROBEntry 328 s0_rep_carry := src.rep_info.rep_carry 329 s0_mshrid := src.rep_info.mshr_id 330 s0_isFirstIssue := false.B 331 s0_fast_rep := true.B 332 s0_ld_rep := src.isLoadReplay 333 s0_l2l_fwd := false.B 334 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 335 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 336 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 337 s0_sched_idx := src.schedIndex 338 } 339 340 def fromNormalReplaySource(src: LsPipelineBundle) = { 341 s0_vaddr := src.vaddr 342 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 343 s0_uop := src.uop 344 s0_try_l2l := false.B 345 s0_has_rob_entry := true.B 346 s0_rep_carry := src.replayCarry 347 s0_mshrid := src.mshrid 348 s0_isFirstIssue := false.B 349 s0_fast_rep := false.B 350 s0_ld_rep := true.B 351 s0_l2l_fwd := false.B 352 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 353 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 354 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 355 s0_sched_idx := src.schedIndex 356 } 357 358 def fromPrefetchSource(src: L1PrefetchReq) = { 359 s0_vaddr := src.getVaddr() 360 s0_mask := 0.U 361 s0_uop := DontCare 362 s0_try_l2l := false.B 363 s0_has_rob_entry := false.B 364 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 365 s0_mshrid := 0.U 366 s0_isFirstIssue := false.B 367 s0_fast_rep := false.B 368 s0_ld_rep := false.B 369 s0_l2l_fwd := false.B 370 s0_prf := true.B 371 s0_prf_rd := !src.is_store 372 s0_prf_wr := src.is_store 373 s0_sched_idx := 0.U 374 } 375 376 def fromIntIssueSource(src: MemExuInput) = { 377 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 378 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 379 s0_uop := src.uop 380 s0_try_l2l := false.B 381 s0_has_rob_entry := true.B 382 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 383 s0_mshrid := 0.U 384 s0_isFirstIssue := true.B 385 s0_fast_rep := false.B 386 s0_ld_rep := false.B 387 s0_l2l_fwd := false.B 388 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 389 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 390 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 391 s0_sched_idx := 0.U 392 } 393 394 def fromVecIssueSource(src: VecPipeBundle) = { 395 // For now, vector port handles only vector store flows 396 s0_vaddr := src.vaddr 397 s0_mask := src.mask 398 s0_uop := src.uop 399 s0_try_l2l := false.B 400 s0_has_rob_entry := true.B 401 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 402 s0_mshrid := 0.U 403 // s0_isFirstIssue := src.isFirstIssue 404 s0_fast_rep := false.B 405 s0_ld_rep := false.B 406 s0_l2l_fwd := false.B 407 s0_prf := false.B 408 s0_prf_rd := false.B 409 s0_prf_wr := false.B 410 s0_sched_idx := 0.U 411 412 s0_isvec := true.B 413 s0_vecActive := io.vec_stu_io.in.bits.vecActive 414 // s0_flowPtr := io.vec_stu_io.in.bits.flowPtr 415 // s0_isLastElem := io.vec_stu_io.in.bits.isLastElem 416 } 417 418 def fromLoadToLoadSource(src: LoadToLoadIO) = { 419 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 420 s0_mask := genVWmask(s0_vaddr, io.ldu_io.ld_fast_fuOpType(1, 0)) 421 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 422 // Assume the pointer chasing is always ld. 423 s0_uop.fuOpType := io.ldu_io.ld_fast_fuOpType 424 s0_try_l2l := true.B 425 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 426 // because these signals will be updated in S1 427 s0_has_rob_entry := false.B 428 s0_mshrid := 0.U 429 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 430 s0_isFirstIssue := true.B 431 s0_fast_rep := false.B 432 s0_ld_rep := false.B 433 s0_l2l_fwd := true.B 434 s0_prf := false.B 435 s0_prf_rd := false.B 436 s0_prf_wr := false.B 437 s0_sched_idx := 0.U 438 } 439 440 // set default 441 s0_uop := DontCare 442 when (s0_src_select_vec(super_rep_idx)) { fromNormalReplaySource(io.ldu_io.replay.bits) } 443 .elsewhen (s0_src_select_vec(fast_rep_idx)) { fromFastReplaySource(io.ldu_io.fast_rep_in.bits) } 444 .elsewhen (s0_src_select_vec(lsq_rep_idx)) { fromNormalReplaySource(io.ldu_io.replay.bits) } 445 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.ldu_io.prefetch_req.bits) } 446 .elsewhen (s0_src_select_vec(int_iss_idx)) { fromIntIssueSource(io.lsin.bits) } 447 .elsewhen (s0_src_select_vec(vec_iss_idx)) { fromVecIssueSource(io.vec_stu_io.in.bits) } 448 .otherwise { 449 if (EnableLoadToLoadForward) { 450 fromLoadToLoadSource(io.ldu_io.l2l_fwd_in) 451 } else { 452 fromNullSource() 453 } 454 } 455 456 // address align check 457 val s0_addr_aligned = LookupTree(Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 458 "b00".U -> true.B, //b 459 "b01".U -> (s0_vaddr(0) === 0.U), //h 460 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 461 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 462 ))// may broken if use it in feature 463 464 // accept load flow if dcache ready (tlb is always ready) 465 // TODO: prefetch need writeback to loadQueueFlag 466 s0_out := DontCare 467 s0_out.vaddr := s0_vaddr 468 s0_out.mask := s0_mask 469 s0_out.uop := s0_uop 470 s0_out.isFirstIssue := s0_isFirstIssue 471 s0_out.hasROBEntry := s0_has_rob_entry 472 s0_out.isPrefetch := s0_prf 473 s0_out.isHWPrefetch := s0_hw_prf 474 s0_out.isFastReplay := s0_fast_rep 475 s0_out.isLoadReplay := s0_ld_rep 476 s0_out.isFastPath := s0_l2l_fwd 477 s0_out.mshrid := s0_mshrid 478 s0_out.isvec := s0_isvec 479 s0_out.isLastElem := s0_isLastElem 480 s0_out.vecActive := s0_vecActive 481 // s0_out.sflowPtr := s0_flowPtr 482 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_ld_flow 483 s0_out.uop.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned && !s0_ld_flow 484 s0_out.forward_tlDchannel := s0_src_select_vec(super_rep_idx) 485 when(io.tlb.req.valid && s0_isFirstIssue) { 486 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 487 }.otherwise{ 488 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 489 } 490 s0_out.schedIndex := s0_sched_idx 491 492 // load fast replay 493 io.ldu_io.fast_rep_in.ready := (s0_can_go && io.ldu_io.dcache.req.ready && s0_src_ready_vec(fast_rep_idx)) 494 495 // load flow source ready 496 // cache missed load has highest priority 497 // always accept cache missed load flow from load replay queue 498 io.ldu_io.replay.ready := (s0_can_go && io.ldu_io.dcache.req.ready && (s0_src_ready_vec(lsq_rep_idx) && !s0_rep_stall || s0_src_select_vec(super_rep_idx))) 499 500 // accept load flow from rs when: 501 // 1) there is no lsq-replayed load 502 // 2) there is no fast replayed load 503 // 3) there is no high confidence prefetch request 504 io.lsin.ready := (s0_can_go && 505 Mux(FuType.isLoad(io.lsin.bits.uop.fuType), io.ldu_io.dcache.req.ready, 506 (if (StorePrefetchL1Enabled) io.stu_io.dcache.req.ready else true.B)) && s0_src_ready_vec(int_iss_idx)) 507 io.vec_stu_io.in.ready := s0_can_go && io.ldu_io.dcache.req.ready && s0_src_ready_vec(vec_iss_idx) 508 509 510 // for hw prefetch load flow feedback, to be added later 511 // io.prefetch_in.ready := s0_hw_prf_select 512 513 // dcache replacement extra info 514 // TODO: should prefetch load update replacement? 515 io.ldu_io.dcache.replacementUpdated := Mux(s0_src_select_vec(lsq_rep_idx) || s0_src_select_vec(super_rep_idx), io.ldu_io.replay.bits.replacementUpdated, false.B) 516 517 io.stu_io.prefetch_req.ready := s1_ready && io.stu_io.dcache.req.ready && !io.lsin.valid 518 519 // load debug 520 XSDebug(io.ldu_io.dcache.req.fire && s0_ld_flow, 521 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 522 ) 523 XSDebug(s0_valid && s0_ld_flow, 524 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lqIdx ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 525 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 526 527 // store debug 528 XSDebug(io.stu_io.dcache.req.fire && !s0_ld_flow, 529 p"[DCACHE STORE REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 530 ) 531 XSDebug(s0_valid && !s0_ld_flow, 532 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, sqIdx ${Hexadecimal(s0_out.uop.sqIdx.asUInt)}, " + 533 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 534 535 536 // Pipeline 537 // -------------------------------------------------------------------------------- 538 // stage 1 539 // -------------------------------------------------------------------------------- 540 // TLB resp (send paddr to dcache) 541 val s1_valid = RegInit(false.B) 542 val s1_in = Wire(new LqWriteBundle) 543 val s1_out = Wire(new LqWriteBundle) 544 val s1_kill = Wire(Bool()) 545 val s1_can_go = s2_ready 546 val s1_fire = s1_valid && !s1_kill && s1_can_go 547 val s1_ld_flow = RegNext(s0_ld_flow) 548 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 549 val s1_isLastElem = RegEnable(s0_out.isLastElem, false.B, s0_fire) 550 551 s1_ready := !s1_valid || s1_kill || s2_ready 552 when (s0_fire) { s1_valid := true.B } 553 .elsewhen (s1_fire) { s1_valid := false.B } 554 .elsewhen (s1_kill) { s1_valid := false.B } 555 s1_in := RegEnable(s0_out, s0_fire) 556 557 val s1_fast_rep_dly_err = RegNext(io.ldu_io.fast_rep_in.bits.delayedLoadError) 558 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 559 val s1_l2l_fwd_dly_err = RegNext(io.ldu_io.l2l_fwd_in.dly_ld_err) 560 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 561 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 562 val s1_vaddr_hi = Wire(UInt()) 563 val s1_vaddr_lo = Wire(UInt()) 564 val s1_vaddr = Wire(UInt()) 565 val s1_paddr_dup_lsu = Wire(UInt()) 566 val s1_paddr_dup_dcache = Wire(UInt()) 567 val s1_ld_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 568 val s1_st_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR // af & pf exception were modified below. 569 val s1_exception = (s1_ld_flow && s1_ld_exception) || (!s1_ld_flow && s1_st_exception) 570 val s1_tlb_miss = io.tlb.resp.bits.miss 571 val s1_prf = s1_in.isPrefetch 572 val s1_hw_prf = s1_in.isHWPrefetch 573 val s1_sw_prf = s1_prf && !s1_hw_prf 574 val s1_tlb_memidx = io.tlb.resp.bits.memidx 575 576 // mmio cbo decoder 577 val s1_mmio_cbo = (s1_in.uop.fuOpType === LSUOpType.cbo_clean || 578 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 579 s1_in.uop.fuOpType === LSUOpType.cbo_inval) && !s1_ld_flow && !s1_prf 580 val s1_mmio = s1_mmio_cbo 581 582 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 583 s1_vaddr_lo := s1_in.vaddr(5, 0) 584 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 585 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 586 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 587 588 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && 589 s1_tlb_memidx.idx === s1_in.uop.lqIdx.value && s1_ld_flow) { 590 // printf("Load idx = %d\n", s1_tlb_memidx.idx) 591 s1_out.uop.debugInfo.tlbRespTime := GTimer() 592 } .elsewhen(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && 593 s1_tlb_memidx.idx === s1_out.uop.sqIdx.value && !s1_ld_flow) { 594 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 595 s1_out.uop.debugInfo.tlbRespTime := GTimer() 596 } 597 598 io.tlb.req_kill := s1_kill 599 io.tlb.resp.ready := true.B 600 601 io.ldu_io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 602 io.ldu_io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 603 io.ldu_io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 604 io.ldu_io.dcache.s1_kill_data_read := s1_kill || s1_tlb_miss 605 606 // store to load forwarding 607 io.ldu_io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 608 io.ldu_io.sbuffer.vaddr := s1_vaddr 609 io.ldu_io.sbuffer.paddr := s1_paddr_dup_lsu 610 io.ldu_io.sbuffer.uop := s1_in.uop 611 io.ldu_io.sbuffer.sqIdx := s1_in.uop.sqIdx 612 io.ldu_io.sbuffer.mask := s1_in.mask 613 io.ldu_io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 614 615 io.ldu_io.ubuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 616 io.ldu_io.ubuffer.vaddr := s1_vaddr 617 io.ldu_io.ubuffer.paddr := s1_paddr_dup_lsu 618 io.ldu_io.ubuffer.uop := s1_in.uop 619 io.ldu_io.ubuffer.sqIdx := s1_in.uop.sqIdx 620 io.ldu_io.ubuffer.mask := s1_in.mask 621 io.ldu_io.ubuffer.pc := s1_in.uop.pc // FIXME: remove it 622 623 io.ldu_io.vec_forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 624 io.ldu_io.vec_forward.vaddr := s1_vaddr 625 io.ldu_io.vec_forward.paddr := s1_paddr_dup_lsu 626 io.ldu_io.vec_forward.uop := s1_in.uop 627 io.ldu_io.vec_forward.sqIdx := s1_in.uop.sqIdx 628 io.ldu_io.vec_forward.mask := s1_in.mask 629 io.ldu_io.vec_forward.pc := s1_in.uop.pc // FIXME: remove it 630 631 io.ldu_io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 632 io.ldu_io.lsq.forward.vaddr := s1_vaddr 633 io.ldu_io.lsq.forward.paddr := s1_paddr_dup_lsu 634 io.ldu_io.lsq.forward.uop := s1_in.uop 635 io.ldu_io.lsq.forward.sqIdx := s1_in.uop.sqIdx 636 io.ldu_io.lsq.forward.sqIdxMask := 0.U 637 io.ldu_io.lsq.forward.mask := s1_in.mask 638 io.ldu_io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 639 640 // st-ld violation query 641 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 642 io.ldu_io.stld_nuke_query(w).valid && // query valid 643 isAfter(s1_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 644 // TODO: Fix me when vector instruction 645 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 646 (s1_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 647 })).asUInt.orR && !s1_tlb_miss && s1_ld_flow 648 649 s1_out := s1_in 650 s1_out.vaddr := s1_vaddr 651 s1_out.paddr := s1_paddr_dup_lsu 652 s1_out.tlbMiss := s1_tlb_miss 653 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 654 s1_out.rep_info.debug := s1_in.uop.debugInfo 655 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 656 s1_out.lateKill := s1_late_kill 657 658 // store trigger 659 val storeTrigger = Module(new MemTrigger(MemType.STORE)) 660 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 661 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 662 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 663 storeTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 664 storeTrigger.io.fromLoadStore.vaddr := s1_vaddr 665 storeTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 666 storeTrigger.io.fromLoadStore.mask := s1_in.mask 667 668 when (s1_ld_flow) { 669 when (!s1_late_kill) { 670 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 671 // af & pf exception were modified 672 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 673 s1_out.uop.exceptionVec(loadGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.ld 674 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 675 } .otherwise { 676 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 677 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill 678 } 679 } .otherwise { 680 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 681 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st 682 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 683 s1_out.uop.trigger := storeTrigger.io.toLoadStore.triggerAction 684 s1_out.uop.exceptionVec(breakPoint) := TriggerAction.isExp(storeTrigger.io.toLoadStore.triggerAction) 685 } 686 687 // load trigger 688 val loadTrigger = Module(new MemTrigger(MemType.LOAD)) 689 loadTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 690 loadTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 691 loadTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 692 loadTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 693 loadTrigger.io.fromLoadStore.vaddr := s1_vaddr 694 loadTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 695 loadTrigger.io.fromLoadStore.mask := s1_in.mask 696 697 when (s1_ld_flow) { 698 s1_out.uop.exceptionVec(breakPoint) := TriggerAction.isExp(loadTrigger.io.toLoadStore.triggerAction) 699 s1_out.uop.trigger := loadTrigger.io.toLoadStore.triggerAction 700 } 701 702 // pointer chasing 703 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 704 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 705 val s1_fu_op_type_not_ld = WireInit(false.B) 706 val s1_not_fast_match = WireInit(false.B) 707 val s1_addr_mismatch = WireInit(false.B) 708 val s1_addr_misaligned = WireInit(false.B) 709 val s1_ptr_chasing_canceled = WireInit(false.B) 710 val s1_cancel_ptr_chasing = WireInit(false.B) 711 712 s1_kill := s1_late_kill || 713 s1_cancel_ptr_chasing || 714 s1_in.uop.robIdx.needFlush(io.redirect) || 715 RegEnable(s0_kill, false.B, io.lsin.valid || io.ldu_io.replay.valid || io.ldu_io.l2l_fwd_in.valid || io.ldu_io.fast_rep_in.valid || io.vec_stu_io.in.valid) 716 717 if (EnableLoadToLoadForward) { 718 // Sometimes, we need to cancel the load-load forwarding. 719 // These can be put at S0 if timing is bad at S1. 720 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 721 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ldu_io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 722 // Case 1: the address is misaligned, kill s1 723 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 724 "b00".U -> false.B, //b 725 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 726 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 727 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 728 )) 729 // Case 2: this load-load uop is cancelled 730 s1_ptr_chasing_canceled := !io.lsin.valid || FuType.isStore(io.lsin.bits.uop.fuType) 731 732 when (s1_try_ptr_chasing) { 733 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 734 735 s1_in.uop := io.lsin.bits.uop 736 s1_in.isFirstIssue := io.lsin.bits.isFirstIssue 737 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 738 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 739 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 740 741 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 742 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 743 s1_in.uop.debugInfo.tlbRespTime := GTimer() 744 } 745 when (!s1_cancel_ptr_chasing) { 746 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.ldu_io.replay.fire && !io.ldu_io.fast_rep_in.fire && !(s0_src_valid_vec(high_pf_idx) && io.canAcceptHighConfPrefetch) 747 when (s1_try_ptr_chasing) { 748 io.lsin.ready := true.B 749 } 750 } 751 } 752 753 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 754 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 755 // to enable load-load, sqIdxMask must be calculated based on lsin.uop 756 // If the timing here is not OK, load-load forwarding has to be disabled. 757 // Or we calculate sqIdxMask at RS?? 758 io.ldu_io.lsq.forward.sqIdxMask := s1_sqIdx_mask 759 if (EnableLoadToLoadForward) { 760 when (s1_try_ptr_chasing) { 761 io.ldu_io.lsq.forward.sqIdxMask := UIntToMask(io.lsin.bits.uop.sqIdx.value, StoreQueueSize) 762 } 763 } 764 765 io.ldu_io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel && s1_ld_flow 766 io.ldu_io.forward_mshr.mshrid := s1_out.mshrid 767 io.ldu_io.forward_mshr.paddr := s1_out.paddr 768 769 io.ldu_io.wakeup.valid := s0_fire && s0_ld_flow && (s0_src_select_vec(super_rep_idx) || s0_src_select_vec(fast_rep_idx) || s0_src_select_vec(lsq_rep_idx) || s0_src_select_vec(int_iss_idx)) 770 io.ldu_io.wakeup.bits := s0_uop 771 772 io.stu_io.dcache.s1_kill := s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect) 773 io.stu_io.dcache.s1_paddr := s1_paddr_dup_dcache 774 775 776 // load debug 777 XSDebug(s1_valid && s1_ld_flow, 778 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 779 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 780 781 // store debug 782 XSDebug(s1_valid && !s1_ld_flow, 783 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.sqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 784 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 785 786 // store out 787 io.stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && !s1_isvec 788 io.stu_io.lsq.bits := s1_out 789 io.stu_io.lsq.bits.miss := s1_tlb_miss 790 791 io.vec_stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && s1_isvec 792 io.vec_stu_io.lsq.bits := s1_out 793 io.vec_stu_io.lsq.bits.miss := s1_tlb_miss 794 io.vec_stu_io.lsq.bits.isLastElem := s1_isLastElem 795 796 io.stu_io.st_mask_out.valid := s1_valid && !s1_ld_flow && !s1_prf 797 io.stu_io.st_mask_out.bits.mask := s1_out.mask 798 io.stu_io.st_mask_out.bits.sqIdx := s1_out.uop.sqIdx 799 800 io.stu_io.issue.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf && !s1_isvec 801 io.stu_io.issue.bits := RegEnable(io.lsin.bits, io.lsin.fire) 802 803 // st-ld violation dectect request 804 io.stu_io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf 805 io.stu_io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 806 io.stu_io.stld_nuke_query.bits.paddr := s1_paddr_dup_lsu 807 io.stu_io.stld_nuke_query.bits.mask := s1_in.mask 808 809 // Pipeline 810 // -------------------------------------------------------------------------------- 811 // stage 2 812 // -------------------------------------------------------------------------------- 813 // s2: DCache resp 814 val s2_valid = RegInit(false.B) 815 val s2_in = Wire(new LqWriteBundle) 816 val s2_out = Wire(new LqWriteBundle) 817 val s2_kill = Wire(Bool()) 818 val s2_can_go = s3_ready 819 val s2_fire = s2_valid && !s2_kill && s2_can_go 820 val s2_isvec = RegEnable(s1_isvec, false.B, s1_fire) 821 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 822 val s2_paddr = RegEnable(s1_paddr_dup_lsu, s1_fire) 823 824 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 825 s2_ready := !s2_valid || s2_kill || s3_ready 826 when (s1_fire) { s2_valid := true.B } 827 .elsewhen (s2_fire) { s2_valid := false.B } 828 .elsewhen (s2_kill) { s2_valid := false.B } 829 s2_in := RegEnable(s1_out, s1_fire) 830 831 val s2_pmp = WireInit(io.pmp) 832 833 val s2_prf = s2_in.isPrefetch 834 val s2_hw_prf = s2_in.isHWPrefetch 835 val s2_ld_flow = RegEnable(s1_ld_flow, s1_fire) 836 837 // exception that may cause load addr to be invalid / illegal 838 // if such exception happen, that inst and its exception info 839 // will be force writebacked to rob 840 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 841 when (s2_ld_flow) { 842 when (!s2_in.lateKill) { 843 s2_exception_vec(loadAccessFault) := s2_vecActive && ( 844 s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld || 845 s2_fwd_frm_d_chan && s2_d_corrupt || 846 s2_fwd_frm_mshr && s2_mshr_corrupt 847 ) 848 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 849 when (s2_prf || s2_in.tlbMiss) { 850 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 851 } 852 } 853 } .otherwise { 854 s2_exception_vec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 855 when (s2_prf || s2_in.tlbMiss) { 856 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 857 } 858 } 859 val s2_ld_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_ld_flow 860 val s2_st_exception = ExceptionNO.selectByFu(s2_exception_vec, StaCfg).asUInt.orR && !s2_ld_flow 861 val s2_exception = s2_ld_exception || s2_st_exception 862 863 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan, s2_d_corrupt) = io.ldu_io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 864 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr, s2_mshr_corrupt) = io.ldu_io.forward_mshr.forward() 865 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 866 867 // writeback access fault caused by ecc error / bus error 868 // * ecc data error is slow to generate, so we will not use it until load stage 3 869 // * in load stage 3, an extra signal io.load_error will be used to 870 val s2_actually_mmio = s2_pmp.mmio 871 val s2_ld_mmio = !s2_prf && 872 s2_actually_mmio && 873 !s2_exception && 874 !s2_in.tlbMiss && 875 s2_ld_flow 876 val s2_st_mmio = !s2_prf && 877 (RegNext(s1_mmio) || s2_pmp.mmio) && 878 !s2_exception && 879 !s2_in.tlbMiss && 880 !s2_ld_flow 881 val s2_st_atomic = !s2_prf && 882 (RegNext(s1_mmio) || s2_pmp.atomic) && 883 !s2_exception && 884 !s2_in.tlbMiss && 885 !s2_ld_flow 886 val s2_full_fwd = Wire(Bool()) 887 val s2_mem_amb = s2_in.uop.storeSetHit && 888 io.ldu_io.lsq.forward.addrInvalid 889 890 val s2_tlb_miss = s2_in.tlbMiss 891 val s2_fwd_fail = io.ldu_io.lsq.forward.dataInvalid || io.ldu_io.vec_forward.dataInvalid 892 val s2_dcache_miss = io.ldu_io.dcache.resp.bits.miss && 893 !s2_fwd_frm_d_chan_or_mshr && 894 !s2_full_fwd 895 896 val s2_mq_nack = io.ldu_io.dcache.s2_mq_nack && 897 !s2_fwd_frm_d_chan_or_mshr && 898 !s2_full_fwd 899 900 val s2_bank_conflict = io.ldu_io.dcache.s2_bank_conflict && 901 !s2_fwd_frm_d_chan_or_mshr && 902 !s2_full_fwd 903 904 val s2_wpu_pred_fail = io.ldu_io.dcache.s2_wpu_pred_fail && 905 !s2_fwd_frm_d_chan_or_mshr && 906 !s2_full_fwd 907 908 val s2_rar_nack = io.ldu_io.lsq.ldld_nuke_query.req.valid && 909 !io.ldu_io.lsq.ldld_nuke_query.req.ready 910 911 val s2_raw_nack = io.ldu_io.lsq.stld_nuke_query.req.valid && 912 !io.ldu_io.lsq.stld_nuke_query.req.ready 913 914 // st-ld violation query 915 // NeedFastRecovery Valid when 916 // 1. Fast recovery query request Valid. 917 // 2. Load instruction is younger than requestors(store instructions). 918 // 3. Physical address match. 919 // 4. Data contains. 920 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 921 io.ldu_io.stld_nuke_query(w).valid && // query valid 922 isAfter(s2_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 923 // TODO: Fix me when vector instruction 924 (s2_in.paddr(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 925 (s2_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 926 })).asUInt.orR && s2_ld_flow || s2_in.rep_info.nuke 927 928 val s2_cache_handled = io.ldu_io.dcache.resp.bits.handled 929 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 930 io.ldu_io.dcache.resp.bits.tag_error 931 932 val s2_troublem = !s2_exception && 933 !s2_ld_mmio && 934 !s2_prf && 935 !s2_in.lateKill && 936 s2_ld_flow 937 938 io.ldu_io.dcache.resp.ready := true.B 939 io.stu_io.dcache.resp.ready := true.B 940 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_ld_mmio || s2_prf || s2_in.lateKill) && s2_ld_flow 941 assert(!(s2_valid && (s2_dcache_should_resp && !io.ldu_io.dcache.resp.valid)), "DCache response got lost") 942 943 // fast replay require 944 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 945 val s2_nuke_fast_rep = !s2_mq_nack && 946 !s2_dcache_miss && 947 !s2_bank_conflict && 948 !s2_wpu_pred_fail && 949 !s2_rar_nack && 950 !s2_raw_nack && 951 s2_nuke 952 953 val s2_fast_rep = !s2_mem_amb && 954 !s2_tlb_miss && 955 !s2_fwd_fail && 956 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 957 s2_troublem 958 959 // need allocate new entry 960 val s2_can_query = !s2_mem_amb && 961 !s2_tlb_miss && 962 !s2_fwd_fail && 963 !s2_dcache_fast_rep && 964 s2_troublem 965 966 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 967 968 // ld-ld violation require 969 io.ldu_io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 970 io.ldu_io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 971 io.ldu_io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 972 io.ldu_io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 973 io.ldu_io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 974 975 // st-ld violation require 976 io.ldu_io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 977 io.ldu_io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 978 io.ldu_io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 979 io.ldu_io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 980 io.ldu_io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 981 982 // merge forward result 983 // lsq has higher priority than sbuffer 984 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 985 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 986 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.ldu_io.lsq.forward.dataInvalid && !io.ldu_io.vec_forward.dataInvalid 987 // generate XLEN/8 Muxs 988 for (i <- 0 until VLEN / 8) { 989 s2_fwd_mask(i) := io.ldu_io.lsq.forward.forwardMask(i) || io.ldu_io.sbuffer.forwardMask(i) || io.ldu_io.vec_forward.forwardMask(i) || io.ldu_io.ubuffer.forwardMask(i) 990 s2_fwd_data(i) := 991 Mux(io.ldu_io.lsq.forward.forwardMask(i), io.ldu_io.lsq.forward.forwardData(i), 992 Mux(io.ldu_io.vec_forward.forwardMask(i), io.ldu_io.vec_forward.forwardData(i), 993 Mux(io.ldu_io.ubuffer.forwardMask(i), io.ldu_io.ubuffer.forwardData(i), 994 io.ldu_io.sbuffer.forwardData(i)))) 995 } 996 997 XSDebug(s2_fire && s2_ld_flow, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 998 s2_in.uop.pc, 999 io.ldu_io.lsq.forward.forwardData.asUInt, io.ldu_io.lsq.forward.forwardMask.asUInt, 1000 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 1001 ) 1002 1003 // 1004 s2_out := s2_in 1005 s2_out.data := 0.U // data will be generated in load s3 1006 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception && s2_ld_flow 1007 s2_out.mmio := s2_ld_mmio || s2_st_mmio 1008 s2_out.atomic := s2_st_atomic 1009 s2_out.uop.flushPipe := false.B 1010 s2_out.uop.exceptionVec := s2_exception_vec 1011 s2_out.forwardMask := s2_fwd_mask 1012 s2_out.forwardData := s2_fwd_data 1013 s2_out.handledByMSHR := s2_cache_handled 1014 s2_out.miss := s2_dcache_miss && s2_troublem 1015 s2_out.feedbacked := io.feedback_fast.valid && !io.feedback_fast.bits.hit 1016 1017 // Generate replay signal caused by: 1018 // * st-ld violation check 1019 // * tlb miss 1020 // * dcache replay 1021 // * forward data invalid 1022 // * dcache miss 1023 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 1024 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 1025 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 1026 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 1027 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 1028 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 1029 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 1030 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 1031 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 1032 s2_out.rep_info.nuke := s2_nuke && s2_troublem 1033 s2_out.rep_info.full_fwd := s2_data_fwded 1034 s2_out.rep_info.data_inv_sq_idx := Mux(io.ldu_io.vec_forward.dataInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.dataInvalidSqIdx) 1035 s2_out.rep_info.addr_inv_sq_idx := Mux(io.ldu_io.vec_forward.addrInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.addrInvalidSqIdx) 1036 s2_out.rep_info.rep_carry := io.ldu_io.dcache.resp.bits.replayCarry 1037 s2_out.rep_info.mshr_id := io.ldu_io.dcache.resp.bits.mshr_id 1038 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 1039 s2_out.rep_info.debug := s2_in.uop.debugInfo 1040 s2_out.rep_info.tlb_id := io.ldu_io.tlb_hint.id 1041 s2_out.rep_info.tlb_full := io.ldu_io.tlb_hint.full 1042 1043 // if forward fail, replay this inst from fetch 1044 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 1045 // if ld-ld violation is detected, replay from this inst from fetch 1046 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_ld_mmio && !s2_is_prefetch && !s2_in.tlbMiss 1047 // io.out.bits.uop.replayInst := false.B 1048 1049 // to be removed 1050 val s2_ld_need_fb = !s2_in.isLoadReplay && // already feedbacked 1051 io.ldu_io.lq_rep_full && // LoadQueueReplay is full 1052 s2_out.rep_info.need_rep && // need replay 1053 !s2_exception && // no exception is triggered 1054 !s2_hw_prf && // not hardware prefetch 1055 !s2_isvec 1056 val s2_st_need_fb = !s2_ld_flow && !s2_hw_prf && !s2_isvec 1057 io.feedback_fast.valid := s2_valid && (s2_ld_need_fb || s2_st_need_fb) 1058 io.feedback_fast.bits.hit := Mux(s2_ld_flow, false.B, !s2_tlb_miss) 1059 io.feedback_fast.bits.flushState := s2_in.ptwBack 1060 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 1061 io.feedback_fast.bits.sourceType := Mux(s2_ld_flow, RSFeedbackType.lrqFull, RSFeedbackType.tlbMiss) 1062 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 1063 1064 val s2_vec_feedback = Wire(Valid(new VSFQFeedback)) 1065 s2_vec_feedback.valid := s2_valid && !s2_ld_flow && !s2_hw_prf && s2_isvec 1066 // s2_vec_feedback.bits.flowPtr := s2_out.sflowPtr 1067 s2_vec_feedback.bits.hit := !s2_tlb_miss 1068 s2_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 1069 s2_vec_feedback.bits.paddr := s2_paddr 1070 s2_vec_feedback.bits.mmio := s2_st_mmio 1071 s2_vec_feedback.bits.atomic := s2_st_mmio 1072 s2_vec_feedback.bits.exceptionVec := s2_exception_vec 1073 1074 io.stu_io.lsq_replenish := s2_out 1075 io.stu_io.lsq_replenish.miss := io.ldu_io.dcache.resp.fire && io.ldu_io.dcache.resp.bits.miss 1076 1077 io.ldu_io.ldCancel.ld1Cancel := false.B 1078 1079 // fast wakeup 1080 io.ldu_io.fast_uop.valid := RegNext( 1081 !io.ldu_io.dcache.s1_disable_fast_wakeup && 1082 s1_valid && 1083 !s1_kill && 1084 !io.tlb.resp.bits.miss && 1085 !io.ldu_io.lsq.forward.dataInvalidFast 1086 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_ld_mmio && s2_ld_flow) && !s2_isvec 1087 io.ldu_io.fast_uop.bits := RegNext(s1_out.uop) 1088 1089 // 1090 io.ldu_io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 1091 1092 // prefetch train 1093 io.s0_prefetch_spec := s0_fire 1094 io.s1_prefetch_spec := s1_fire 1095 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 1096 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 1097 io.prefetch_train.bits.miss := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.miss, io.stu_io.dcache.resp.bits.miss) // TODO: use trace with bank conflict? 1098 io.prefetch_train.bits.meta_prefetch := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_prefetch, false.B) 1099 io.prefetch_train.bits.meta_access := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_access, false.B) 1100 1101 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio && s2_ld_flow 1102 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1103 io.prefetch_train_l1.bits.miss := io.ldu_io.dcache.resp.bits.miss 1104 io.prefetch_train_l1.bits.meta_prefetch := io.ldu_io.dcache.resp.bits.meta_prefetch 1105 io.prefetch_train_l1.bits.meta_access := io.ldu_io.dcache.resp.bits.meta_access 1106 if (env.FPGAPlatform){ 1107 io.ldu_io.dcache.s0_pc := DontCare 1108 io.ldu_io.dcache.s1_pc := DontCare 1109 io.ldu_io.dcache.s2_pc := DontCare 1110 }else{ 1111 io.ldu_io.dcache.s0_pc := s0_out.uop.pc 1112 io.ldu_io.dcache.s1_pc := s1_out.uop.pc 1113 io.ldu_io.dcache.s2_pc := s2_out.uop.pc 1114 } 1115 io.ldu_io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 1116 io.stu_io.dcache.s2_kill := s2_pmp.st || s2_actually_mmio || s2_kill 1117 io.stu_io.dcache.s2_pc := s2_out.uop.pc 1118 1119 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready && s1_ld_flow 1120 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1121 s2_ld_valid_dup := 0x0.U(6.W) 1122 when (s1_ld_left_fire && !s1_out.isHWPrefetch && s1_ld_flow) { s2_ld_valid_dup := 0x3f.U(6.W) } 1123 when (s1_kill || s1_out.isHWPrefetch || !s1_ld_flow) { s2_ld_valid_dup := 0x0.U(6.W) } 1124 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch) || RegNext(!s1_ld_flow))) 1125 1126 // Pipeline 1127 // -------------------------------------------------------------------------------- 1128 // stage 3 1129 // -------------------------------------------------------------------------------- 1130 // writeback and update load queue 1131 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1132 val s3_in = RegEnable(s2_out, s2_fire) 1133 val s3_out = Wire(Valid(new MemExuOutput)) 1134 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1135 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1136 val s3_fast_rep = Wire(Bool()) 1137 val s3_ld_flow = RegNext(s2_ld_flow) 1138 val s3_troublem = RegNext(s2_troublem) 1139 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1140 val s3_isvec = RegNext(s2_isvec) 1141 s3_ready := !s3_valid || s3_kill || sx_can_go 1142 1143 // s3 load fast replay 1144 io.ldu_io.fast_rep_out.valid := s3_valid && 1145 s3_fast_rep && 1146 !s3_in.uop.robIdx.needFlush(io.redirect) && 1147 s3_ld_flow && 1148 !s3_isvec 1149 io.ldu_io.fast_rep_out.bits := s3_in 1150 1151 io.ldu_io.lsq.ldin.valid := s3_valid && 1152 (!s3_fast_rep || !io.ldu_io.fast_rep_out.ready) && 1153 !s3_in.feedbacked && 1154 !s3_in.lateKill && 1155 s3_ld_flow 1156 io.ldu_io.lsq.ldin.bits := s3_in 1157 io.ldu_io.lsq.ldin.bits.miss := s3_in.miss 1158 1159 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1160 io.ldu_io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1161 io.ldu_io.lsq.ldin.bits.replacementUpdated := io.ldu_io.dcache.resp.bits.replacementUpdated 1162 io.ldu_io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1163 1164 val s3_dly_ld_err = 1165 if (EnableAccurateLoadError) { 1166 (s3_in.lateKill || io.ldu_io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1167 } else { 1168 WireInit(false.B) 1169 } 1170 io.ldu_io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1171 io.ldu_io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1172 io.ldu_io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1173 1174 val s3_vp_match_fail = RegNext(io.ldu_io.lsq.forward.matchInvalid || io.ldu_io.sbuffer.matchInvalid || io.ldu_io.ubuffer.matchInvalid) && s3_troublem 1175 val s3_ldld_rep_inst = 1176 io.ldu_io.lsq.ldld_nuke_query.resp.valid && 1177 io.ldu_io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1178 RegNext(io.csrCtrl.ldld_vio_check_enable) 1179 1180 val s3_rep_info = WireInit(s3_in.rep_info) 1181 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && s3_troublem 1182 val s3_rep_frm_fetch = s3_vp_match_fail 1183 val s3_flushPipe = s3_ldld_rep_inst 1184 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1185 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1186 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1187 s3_troublem 1188 1189 val s3_ld_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_ld_flow 1190 val s3_st_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, StaCfg).asUInt.orR && !s3_ld_flow 1191 val s3_exception = s3_ld_exception || s3_st_exception 1192 when ((s3_ld_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1193 io.ldu_io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1194 } .otherwise { 1195 io.ldu_io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1196 } 1197 1198 // Int flow, if hit, will be writebacked at s3 1199 s3_out.valid := s3_valid && 1200 (!s3_ld_flow && !s3_in.feedbacked || !io.ldu_io.lsq.ldin.bits.rep_info.need_rep) && !s3_in.mmio 1201 s3_out.bits.uop := s3_in.uop 1202 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_ld_flow 1203 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1204 s3_out.bits.data := s3_in.data 1205 s3_out.bits.debug.isMMIO := s3_in.mmio 1206 s3_out.bits.debug.isNC := s3_in.nc 1207 s3_out.bits.debug.isPerfCnt := false.B 1208 s3_out.bits.debug.paddr := s3_in.paddr 1209 s3_out.bits.debug.vaddr := s3_in.vaddr 1210 1211 when (s3_force_rep) { 1212 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1213 } 1214 1215 io.ldu_io.rollback.valid := s3_valid && (s3_rep_frm_fetch || s3_flushPipe) && !s3_exception && s3_ld_flow 1216 io.ldu_io.rollback.bits := DontCare 1217 io.ldu_io.rollback.bits.isRVC := s3_out.bits.uop.preDecodeInfo.isRVC 1218 io.ldu_io.rollback.bits.robIdx := s3_out.bits.uop.robIdx 1219 io.ldu_io.rollback.bits.ftqIdx := s3_out.bits.uop.ftqPtr 1220 io.ldu_io.rollback.bits.ftqOffset := s3_out.bits.uop.ftqOffset 1221 io.ldu_io.rollback.bits.level := Mux(s3_rep_frm_fetch, RedirectLevel.flush, RedirectLevel.flushAfter) 1222 io.ldu_io.rollback.bits.cfiUpdate.target := s3_out.bits.uop.pc 1223 io.ldu_io.rollback.bits.debug_runahead_checkpoint_id := s3_out.bits.uop.debugInfo.runahead_checkpoint_id 1224 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1225 io.ldu_io.lsq.ldin.bits.uop := s3_out.bits.uop 1226 1227 val s3_revoke = s3_exception || io.ldu_io.lsq.ldin.bits.rep_info.need_rep 1228 io.ldu_io.lsq.ldld_nuke_query.revoke := s3_revoke 1229 io.ldu_io.lsq.stld_nuke_query.revoke := s3_revoke 1230 1231 // feedback slow 1232 s3_fast_rep := RegNext(s2_fast_rep) && 1233 !s3_in.feedbacked && 1234 !s3_in.lateKill && 1235 !s3_rep_frm_fetch && 1236 !s3_exception 1237 1238 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.ldu_io.fast_rep_out.ready) && !s3_in.feedbacked 1239 1240 // 1241 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting && s3_ld_flow 1242 io.feedback_slow.bits.hit := !io.ldu_io.lsq.ldin.bits.rep_info.need_rep || io.ldu_io.lsq.ldin.ready 1243 io.feedback_slow.bits.flushState := s3_in.ptwBack 1244 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1245 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1246 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1247 1248 io.vec_stu_io.feedbackSlow.valid := RegNext(s2_vec_feedback.valid && !s2_out.uop.robIdx.needFlush(io.redirect)) 1249 io.vec_stu_io.feedbackSlow.bits := RegNext(s2_vec_feedback.bits) 1250 1251 io.ldu_io.ldCancel.ld2Cancel := s3_valid && s3_ld_flow && ( // is load 1252 io.ldu_io.lsq.ldin.bits.rep_info.need_rep || s3_in.mmio // exe fail or is mmio 1253 ) 1254 1255 // data from dcache hit 1256 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1257 s3_ld_raw_data_frm_cache.respDcacheData := io.ldu_io.dcache.resp.bits.data 1258 s3_ld_raw_data_frm_cache.forward_D := s2_fwd_frm_d_chan 1259 s3_ld_raw_data_frm_cache.forwardData_D := s2_fwd_data_frm_d_chan 1260 s3_ld_raw_data_frm_cache.forward_mshr := s2_fwd_frm_mshr 1261 s3_ld_raw_data_frm_cache.forwardData_mshr := s2_fwd_data_frm_mshr 1262 s3_ld_raw_data_frm_cache.forward_result_valid := s2_fwd_data_valid 1263 1264 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1265 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1266 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1267 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1268 1269 val s3_merged_data_frm_tlD = RegEnable(s3_ld_raw_data_frm_cache.mergeTLData(), s2_valid) 1270 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergeLsqFwdData(s3_merged_data_frm_tlD) 1271 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1272 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1273 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1274 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1275 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1276 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1277 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1278 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1279 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1280 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1281 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1282 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1283 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1284 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1285 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1286 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1287 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1288 )) 1289 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1290 1291 // FIXME: add 1 cycle delay ? 1292 io.ldout.bits := s3_out.bits 1293 io.ldout.bits.data := s3_ld_data_frm_cache 1294 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && s3_ld_flow && !s3_isvec 1295 1296 // for uncache 1297 io.ldu_io.lsq.uncache.ready := true.B 1298 1299 // fast load to load forward 1300 if (EnableLoadToLoadForward) { 1301 io.ldu_io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill && s3_ld_flow 1302 io.ldu_io.l2l_fwd_out.data := s3_ld_data_frm_cache 1303 io.ldu_io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1304 } else { 1305 io.ldu_io.l2l_fwd_out.valid := false.B 1306 io.ldu_io.l2l_fwd_out.data := DontCare 1307 io.ldu_io.l2l_fwd_out.dly_ld_err := DontCare 1308 } 1309 1310 // hybrid unit writeback to rob 1311 // delay params 1312 val SelectGroupSize = RollbackGroupSize 1313 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 1314 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 1315 val TotalDelayCycles = TotalSelectCycles - 2 1316 1317 // writeback 1318 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 1319 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 1320 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 1321 1322 sx_can_go := sx_ready.head 1323 for (i <- 0 until TotalDelayCycles + 1) { 1324 if (i == 0) { 1325 sx_valid(i) := s3_valid && 1326 !s3_ld_flow && 1327 !s3_in.feedbacked && 1328 !s3_in.mmio 1329 sx_in(i) := s3_out.bits 1330 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 1331 } else { 1332 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 1333 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1334 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 1335 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 1336 1337 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1338 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 1339 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 1340 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 1341 } 1342 } 1343 1344 val sx_last_valid = sx_valid.takeRight(1).head 1345 val sx_last_ready = sx_ready.takeRight(1).head 1346 val sx_last_in = sx_in.takeRight(1).head 1347 1348 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 1349 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) && FuType.isStore(sx_last_in.uop.fuType) 1350 io.stout.bits := sx_last_in 1351 1352 // FIXME: please move this part to LoadQueueReplay 1353 io.ldu_io.debug_ls := DontCare 1354 io.stu_io.debug_ls := DontCare 1355 io.stu_io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch && !s1_ld_flow 1356 io.stu_io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 1357 1358 // Topdown 1359 io.ldu_io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1360 io.ldu_io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1361 io.ldu_io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1362 io.ldu_io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1363 io.ldu_io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1364 io.ldu_io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1365 io.ldu_io.lsTopdownInfo.s2.first_real_miss := io.ldu_io.dcache.resp.bits.real_miss 1366 io.ldu_io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1367 1368 // perf cnt 1369 XSPerfAccumulate("s0_in_valid", io.lsin.valid) 1370 XSPerfAccumulate("s0_in_block", io.lsin.valid && !io.lsin.fire) 1371 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1372 XSPerfAccumulate("s0_lsq_fire_first_issue", io.ldu_io.replay.fire) 1373 XSPerfAccumulate("s0_ldu_fire_first_issue", io.lsin.fire && s0_isFirstIssue) 1374 XSPerfAccumulate("s0_fast_replay_issue", io.ldu_io.fast_rep_in.fire) 1375 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1376 XSPerfAccumulate("s0_stall_ld_dcache", s0_valid && !io.ldu_io.dcache.req.ready) 1377 XSPerfAccumulate("s0_stall_st_dcache", s0_valid && !io.stu_io.dcache.req.ready) 1378 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12)) 1379 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12)) 1380 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1381 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1382 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1383 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1384 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_src_select_vec(int_iss_idx)) 1385 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.ldu_io.prefetch_req.valid && !s0_hw_prf_select) 1386 XSPerfAccumulate("s0_hardware_prefetch_total", io.ldu_io.prefetch_req.valid) 1387 1388 XSPerfAccumulate("s1_in_valid", s1_valid) 1389 XSPerfAccumulate("s1_in_fire", s1_fire) 1390 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1391 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1392 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1393 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1394 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1395 1396 XSPerfAccumulate("s2_in_valid", s2_valid) 1397 XSPerfAccumulate("s2_in_fire", s2_fire) 1398 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1399 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.ldu_io.dcache.resp.bits.miss) 1400 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1401 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1402 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1403 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1404 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1405 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1406 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1407 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1408 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && io.ldu_io.dcache.s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1409 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss) // prefetch req miss in l1 1410 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.ldu_io.dcache.resp.bits.miss) // prefetch req hit in l1 1411 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss && !io.ldu_io.dcache.s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1412 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1413 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1414 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1415 1416 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1417 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1418 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1419 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1420 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1421 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1422 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1423 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1424 1425 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1426 // hardware performance counter 1427 val perfEvents = Seq( 1428 ("load_s0_in_fire ", s0_fire ), 1429 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1430 ("stall_dcache ", s0_valid && s0_can_go && !io.ldu_io.dcache.req.ready ), 1431 ("load_s1_in_fire ", s0_fire ), 1432 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1433 ("load_s2_in_fire ", s1_fire ), 1434 ("load_s2_dcache_miss ", s2_fire && io.ldu_io.dcache.resp.bits.miss ), 1435 ) 1436 generatePerfEvent() 1437} 1438