1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan.ExceptionNO._ 24import xiangshan._ 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 28 29class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 30 val loadIn = ValidIO(new LsPipelineBundle) 31 val ldout = Flipped(DecoupledIO(new ExuOutput)) 32 val loadDataForwarded = Output(Bool()) 33 val needReplayFromRS = Output(Bool()) 34 val forward = new PipeLoadForwardQueryIO 35 val loadViolationQuery = new LoadViolationQueryIO 36 val trigger = Flipped(new LqTriggerIO) 37} 38 39class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 40 // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 41 val data = UInt(XLEN.W) 42 val valid = Bool() 43} 44 45class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 46 val tdata2 = Input(UInt(64.W)) 47 val matchType = Input(UInt(2.W)) 48 val tEnable = Input(Bool()) // timing is calculated before this 49 val addrHit = Output(Bool()) 50 val lastDataHit = Output(Bool()) 51} 52 53// Load Pipeline Stage 0 54// Generate addr, use addr to query DCache and DTLB 55class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParameters{ 56 val io = IO(new Bundle() { 57 val in = Flipped(Decoupled(new ExuInput)) 58 val out = Decoupled(new LsPipelineBundle) 59 val fastpath = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 60 val dtlbReq = DecoupledIO(new TlbReq) 61 val dcacheReq = DecoupledIO(new DCacheWordReq) 62 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 63 val isFirstIssue = Input(Bool()) 64 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 65 }) 66 require(LoadPipelineWidth == exuParameters.LduCnt) 67 68 val s0_uop = io.in.bits.uop 69 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 70 71 val s0_vaddr = WireInit(io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits)) 72 val s0_mask = WireInit(genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0))) 73 74 if (EnableLoadToLoadForward) { 75 // slow vaddr from non-load insts 76 val slowpath_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 77 val slowpath_mask = genWmask(slowpath_vaddr, s0_uop.ctrl.fuOpType(1,0)) 78 79 // fast vaddr from load insts 80 val fastpath_vaddrs = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 81 io.fastpath(i).data + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 82 }))) 83 val fastpath_masks = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 84 genWmask(fastpath_vaddrs(i), s0_uop.ctrl.fuOpType(1,0)) 85 }))) 86 val fastpath_vaddr = Mux1H(io.loadFastMatch, fastpath_vaddrs) 87 val fastpath_mask = Mux1H(io.loadFastMatch, fastpath_masks) 88 89 // select vaddr from 2 alus 90 s0_vaddr := Mux(io.loadFastMatch.orR, fastpath_vaddr, slowpath_vaddr) 91 s0_mask := Mux(io.loadFastMatch.orR, fastpath_mask, slowpath_mask) 92 XSPerfAccumulate("load_to_load_forward", io.loadFastMatch.orR && io.in.fire()) 93 } 94 95 val isSoftPrefetch = LSUOpType.isPrefetch(s0_uop.ctrl.fuOpType) 96 val isSoftPrefetchRead = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_r 97 val isSoftPrefetchWrite = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_w 98 99 // query DTLB 100 io.dtlbReq.valid := io.in.valid 101 io.dtlbReq.bits.vaddr := s0_vaddr 102 io.dtlbReq.bits.cmd := TlbCmd.read 103 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 104 io.dtlbReq.bits.robIdx := s0_uop.robIdx 105 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 106 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 107 108 // query DCache 109 io.dcacheReq.valid := io.in.valid 110 when (isSoftPrefetchRead) { 111 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFR 112 }.elsewhen (isSoftPrefetchWrite) { 113 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFW 114 }.otherwise { 115 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 116 } 117 io.dcacheReq.bits.addr := s0_vaddr 118 io.dcacheReq.bits.mask := s0_mask 119 io.dcacheReq.bits.data := DontCare 120 when(isSoftPrefetch) { 121 io.dcacheReq.bits.instrtype := SOFT_PREFETCH.U 122 }.otherwise { 123 io.dcacheReq.bits.instrtype := LOAD_SOURCE.U 124 } 125 126 // TODO: update cache meta 127 io.dcacheReq.bits.id := DontCare 128 129 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 130 "b00".U -> true.B, //b 131 "b01".U -> (s0_vaddr(0) === 0.U), //h 132 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 133 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 134 )) 135 136 io.out.valid := io.in.valid && io.dcacheReq.ready 137 138 io.out.bits := DontCare 139 io.out.bits.vaddr := s0_vaddr 140 io.out.bits.mask := s0_mask 141 io.out.bits.uop := s0_uop 142 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 143 io.out.bits.rsIdx := io.rsIdx 144 io.out.bits.isFirstIssue := io.isFirstIssue 145 io.out.bits.isSoftPrefetch := isSoftPrefetch 146 147 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 148 149 XSDebug(io.dcacheReq.fire(), 150 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 151 ) 152 XSPerfAccumulate("in_valid", io.in.valid) 153 XSPerfAccumulate("in_fire", io.in.fire) 154 XSPerfAccumulate("in_fire_first_issue", io.in.valid && io.isFirstIssue) 155 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 156 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 157 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 158 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 159 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 160 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 161} 162 163 164// Load Pipeline Stage 1 165// TLB resp (send paddr to dcache) 166class LoadUnit_S1(implicit p: Parameters) extends XSModule { 167 val io = IO(new Bundle() { 168 val in = Flipped(Decoupled(new LsPipelineBundle)) 169 val out = Decoupled(new LsPipelineBundle) 170 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 171 val dcachePAddr = Output(UInt(PAddrBits.W)) 172 val dcacheKill = Output(Bool()) 173 val fastUopKill = Output(Bool()) 174 val dcacheBankConflict = Input(Bool()) 175 val fullForwardFast = Output(Bool()) 176 val sbuffer = new LoadForwardQueryIO 177 val lsq = new PipeLoadForwardQueryIO 178 val loadViolationQueryReq = Decoupled(new LoadViolationQueryReq) 179 val rsFeedback = ValidIO(new RSFeedback) 180 val csrCtrl = Flipped(new CustomCSRCtrlIO) 181 val needLdVioCheckRedo = Output(Bool()) 182 }) 183 184 val s1_uop = io.in.bits.uop 185 val s1_paddr = io.dtlbResp.bits.paddr 186 // af & pf exception were modified below. 187 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, lduCfg).asUInt.orR 188 val s1_tlb_miss = io.dtlbResp.bits.miss 189 val s1_mask = io.in.bits.mask 190 val s1_bank_conflict = io.dcacheBankConflict 191 192 io.out.bits := io.in.bits // forwardXX field will be updated in s1 193 194 io.dtlbResp.ready := true.B 195 196 // TOOD: PMA check 197 io.dcachePAddr := s1_paddr 198 //io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 199 io.dcacheKill := s1_tlb_miss || s1_exception 200 io.fastUopKill := io.dtlbResp.bits.fast_miss || s1_exception 201 202 // load forward query datapath 203 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 204 io.sbuffer.vaddr := io.in.bits.vaddr 205 io.sbuffer.paddr := s1_paddr 206 io.sbuffer.uop := s1_uop 207 io.sbuffer.sqIdx := s1_uop.sqIdx 208 io.sbuffer.mask := s1_mask 209 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 210 211 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 212 io.lsq.vaddr := io.in.bits.vaddr 213 io.lsq.paddr := s1_paddr 214 io.lsq.uop := s1_uop 215 io.lsq.sqIdx := s1_uop.sqIdx 216 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 217 io.lsq.mask := s1_mask 218 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 219 220 // ld-ld violation query 221 io.loadViolationQueryReq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 222 io.loadViolationQueryReq.bits.paddr := s1_paddr 223 io.loadViolationQueryReq.bits.uop := s1_uop 224 225 // Generate forwardMaskFast to wake up insts earlier 226 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 227 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 228 229 // Generate feedback signal caused by: 230 // * dcache bank conflict 231 // * need redo ld-ld violation check 232 val needLdVioCheckRedo = io.loadViolationQueryReq.valid && 233 !io.loadViolationQueryReq.ready && 234 RegNext(io.csrCtrl.ldld_vio_check) 235 io.needLdVioCheckRedo := needLdVioCheckRedo 236 io.rsFeedback.valid := io.in.valid && (s1_bank_conflict || needLdVioCheckRedo) 237 io.rsFeedback.bits.hit := false.B // we have found s1_bank_conflict / re do ld-ld violation check 238 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 239 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 240 io.rsFeedback.bits.sourceType := Mux(s1_bank_conflict, RSFeedbackType.bankConflict, RSFeedbackType.ldVioCheckRedo) 241 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 242 243 // if replay is detected in load_s1, 244 // load inst will be canceled immediately 245 io.out.valid := io.in.valid && !io.rsFeedback.valid 246 io.out.bits.paddr := s1_paddr 247 io.out.bits.tlbMiss := s1_tlb_miss 248 249 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 250 // af & pf exception were modified 251 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 252 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 253 254 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 255 io.out.bits.rsIdx := io.in.bits.rsIdx 256 257 io.out.bits.isSoftPrefetch := io.in.bits.isSoftPrefetch 258 259 io.in.ready := !io.in.valid || io.out.ready 260 261 XSPerfAccumulate("in_valid", io.in.valid) 262 XSPerfAccumulate("in_fire", io.in.fire) 263 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 264 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 265 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 266 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 267} 268 269// Load Pipeline Stage 2 270// DCache resp 271class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 272 val io = IO(new Bundle() { 273 val in = Flipped(Decoupled(new LsPipelineBundle)) 274 val out = Decoupled(new LsPipelineBundle) 275 val rsFeedback = ValidIO(new RSFeedback) 276 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 277 val pmpResp = Flipped(new PMPRespBundle()) 278 val lsq = new LoadForwardQueryIO 279 val dataInvalidSqIdx = Input(UInt()) 280 val sbuffer = new LoadForwardQueryIO 281 val dataForwarded = Output(Bool()) 282 val needReplayFromRS = Output(Bool()) 283 val fullForward = Output(Bool()) 284 val fastpath = Output(new LoadToLoadIO) 285 val dcache_kill = Output(Bool()) 286 val loadViolationQueryResp = Flipped(Valid(new LoadViolationQueryResp)) 287 val csrCtrl = Flipped(new CustomCSRCtrlIO) 288 val sentFastUop = Input(Bool()) 289 }) 290 val isSoftPrefetch = io.in.bits.isSoftPrefetch 291 val excep = WireInit(io.in.bits.uop.cf.exceptionVec) 292 excep(loadAccessFault) := io.in.bits.uop.cf.exceptionVec(loadAccessFault) || io.pmpResp.ld 293 when (isSoftPrefetch) { 294 excep := 0.U.asTypeOf(excep.cloneType) 295 } 296 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, lduCfg).asUInt.orR 297 298 val actually_mmio = io.pmpResp.mmio 299 val s2_uop = io.in.bits.uop 300 val s2_mask = io.in.bits.mask 301 val s2_paddr = io.in.bits.paddr 302 val s2_tlb_miss = io.in.bits.tlbMiss 303 val s2_data_invalid = io.lsq.dataInvalid 304 val s2_mmio = !isSoftPrefetch && actually_mmio && !s2_exception 305 val s2_cache_miss = io.dcacheResp.bits.miss 306 val s2_cache_replay = io.dcacheResp.bits.replay 307 val s2_is_prefetch = io.in.bits.isSoftPrefetch 308 309 // val cnt = RegInit(127.U) 310 // cnt := cnt + io.in.valid.asUInt 311 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 312 313 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 314 // assert(!s2_forward_fail) 315 io.dcache_kill := false.B // move pmp resp kill to outside 316 io.dcacheResp.ready := true.B 317 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio || s2_is_prefetch) 318 assert(!(io.in.valid && (dcacheShouldResp && !io.dcacheResp.valid)), "DCache response got lost") 319 320 // merge forward result 321 // lsq has higher priority than sbuffer 322 val forwardMask = Wire(Vec(8, Bool())) 323 val forwardData = Wire(Vec(8, UInt(8.W))) 324 325 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 326 io.lsq := DontCare 327 io.sbuffer := DontCare 328 io.fullForward := fullForward 329 330 // generate XLEN/8 Muxs 331 for (i <- 0 until XLEN / 8) { 332 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 333 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 334 } 335 336 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 337 s2_uop.cf.pc, 338 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 339 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 340 ) 341 342 // data merge 343 val rdataVec = VecInit((0 until XLEN / 8).map(j => 344 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 345 val rdata = rdataVec.asUInt 346 val rdataSel = LookupTree(s2_paddr(2, 0), List( 347 "b000".U -> rdata(63, 0), 348 "b001".U -> rdata(63, 8), 349 "b010".U -> rdata(63, 16), 350 "b011".U -> rdata(63, 24), 351 "b100".U -> rdata(63, 32), 352 "b101".U -> rdata(63, 40), 353 "b110".U -> rdata(63, 48), 354 "b111".U -> rdata(63, 56) 355 )) 356 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 357 358 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 359 // Inst will be canceled in store queue / lsq, 360 // so we do not need to care about flush in load / store unit's out.valid 361 io.out.bits := io.in.bits 362 io.out.bits.data := rdataPartialLoad 363 // when exception occurs, set it to not miss and let it write back to rob (via int port) 364 if (EnableFastForward) { 365 io.out.bits.miss := s2_cache_miss && 366 !s2_exception && 367 !s2_forward_fail && 368 !fullForward && 369 !s2_is_prefetch 370 } else { 371 io.out.bits.miss := s2_cache_miss && 372 !s2_exception && 373 !s2_forward_fail && 374 !s2_is_prefetch 375 } 376 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 377 // if forward fail, replay this inst from fetch 378 val forwardFailReplay = s2_forward_fail && !s2_mmio 379 // if ld-ld violation is detected, replay from this inst from fetch 380 val ldldVioReplay = io.loadViolationQueryResp.valid && 381 io.loadViolationQueryResp.bits.have_violation && 382 RegNext(io.csrCtrl.ldld_vio_check) 383 io.out.bits.uop.ctrl.replayInst := forwardFailReplay || ldldVioReplay 384 io.out.bits.mmio := s2_mmio 385 io.out.bits.uop.ctrl.flushPipe := s2_mmio && io.sentFastUop 386 io.out.bits.uop.cf.exceptionVec := excep 387 388 // For timing reasons, sometimes we can not let 389 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 390 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 391 // and dcache query is no longer needed. 392 // Such inst will be writebacked from load queue. 393 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 394 // io.out.bits.forwardX will be send to lq 395 io.out.bits.forwardMask := forwardMask 396 // data retbrived from dcache is also included in io.out.bits.forwardData 397 io.out.bits.forwardData := rdataVec 398 399 io.in.ready := io.out.ready || !io.in.valid 400 401 // feedback tlb result to RS 402 io.rsFeedback.valid := io.in.valid 403 when (io.in.bits.isSoftPrefetch) { 404 io.rsFeedback.bits.hit := (!s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception)) 405 }.otherwise { 406 if (EnableFastForward) { 407 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 408 } else { 409 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) && !s2_data_invalid 410 } 411 } 412 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 413 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 414 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 415 Mux(s2_cache_replay, 416 RSFeedbackType.mshrFull, 417 RSFeedbackType.dataInvalid 418 ) 419 ) 420 io.rsFeedback.bits.dataInvalidSqIdx.value := io.dataInvalidSqIdx 421 io.rsFeedback.bits.dataInvalidSqIdx.flag := DontCare 422 423 // s2_cache_replay is quite slow to generate, send it separately to LQ 424 if (EnableFastForward) { 425 io.needReplayFromRS := s2_cache_replay && !fullForward 426 } else { 427 io.needReplayFromRS := s2_cache_replay 428 } 429 430 // fast load to load forward 431 io.fastpath.valid := io.in.valid // for debug only 432 io.fastpath.data := rdata // raw data 433 434 435 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 436 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 437 forwardData.asUInt, forwardMask.asUInt 438 ) 439 440 XSPerfAccumulate("in_valid", io.in.valid) 441 XSPerfAccumulate("in_fire", io.in.fire) 442 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 443 XSPerfAccumulate("dcache_miss", io.in.fire && s2_cache_miss) 444 XSPerfAccumulate("dcache_miss_first_issue", io.in.fire && s2_cache_miss && io.in.bits.isFirstIssue) 445 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 446 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 447 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 448 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 449 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 450 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 451 XSPerfAccumulate("replay_from_fetch_forward", io.out.valid && forwardFailReplay) 452 XSPerfAccumulate("replay_from_fetch_load_vio", io.out.valid && ldldVioReplay) 453} 454 455class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper with HasPerfEvents { 456 val io = IO(new Bundle() { 457 val ldin = Flipped(Decoupled(new ExuInput)) 458 val ldout = Decoupled(new ExuOutput) 459 val redirect = Flipped(ValidIO(new Redirect)) 460 val feedbackSlow = ValidIO(new RSFeedback) 461 val feedbackFast = ValidIO(new RSFeedback) 462 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 463 val isFirstIssue = Input(Bool()) 464 val dcache = new DCacheLoadIO 465 val sbuffer = new LoadForwardQueryIO 466 val lsq = new LoadToLsqIO 467 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 468 val trigger = Vec(3, new LoadUnitTriggerIO) 469 470 val tlb = new TlbRequestIO 471 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 472 473 val fastpathOut = Output(new LoadToLoadIO) 474 val fastpathIn = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 475 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 476 477 val csrCtrl = Flipped(new CustomCSRCtrlIO) 478 }) 479 480 val load_s0 = Module(new LoadUnit_S0) 481 val load_s1 = Module(new LoadUnit_S1) 482 val load_s2 = Module(new LoadUnit_S2) 483 484 load_s0.io.in <> io.ldin 485 load_s0.io.dtlbReq <> io.tlb.req 486 load_s0.io.dcacheReq <> io.dcache.req 487 load_s0.io.rsIdx := io.rsIdx 488 load_s0.io.isFirstIssue := io.isFirstIssue 489 load_s0.io.fastpath := io.fastpathIn 490 load_s0.io.loadFastMatch := io.loadFastMatch 491 492 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 493 494 load_s1.io.dtlbResp <> io.tlb.resp 495 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 496 io.dcache.s1_kill <> load_s1.io.dcacheKill 497 load_s1.io.sbuffer <> io.sbuffer 498 load_s1.io.lsq <> io.lsq.forward 499 load_s1.io.loadViolationQueryReq <> io.lsq.loadViolationQuery.req 500 load_s1.io.dcacheBankConflict <> io.dcache.s1_bank_conflict 501 load_s1.io.csrCtrl <> io.csrCtrl 502 503 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 504 505 io.dcache.s2_kill := load_s2.io.dcache_kill || (io.pmp.ld || io.pmp.mmio) // to kill mmio resp which are redirected 506 load_s2.io.dcacheResp <> io.dcache.resp 507 load_s2.io.pmpResp <> io.pmp 508 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 509 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 510 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 511 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 512 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 513 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 514 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 515 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 516 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 517 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 518 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 519 load_s2.io.fastpath <> io.fastpathOut 520 load_s2.io.dataInvalidSqIdx := io.lsq.forward.dataInvalidSqIdx // provide dataInvalidSqIdx to make wakeup faster 521 load_s2.io.loadViolationQueryResp <> io.lsq.loadViolationQuery.resp 522 load_s2.io.csrCtrl <> io.csrCtrl 523 load_s2.io.sentFastUop := RegEnable(io.fastUop.valid, load_s1.io.out.fire()) // RegNext is also ok 524 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 525 526 // feedback tlb miss / dcache miss queue full 527 io.feedbackSlow.bits := RegNext(load_s2.io.rsFeedback.bits) 528 io.feedbackSlow.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 529 530 // feedback bank conflict to rs 531 io.feedbackFast.bits := load_s1.io.rsFeedback.bits 532 io.feedbackFast.valid := load_s1.io.rsFeedback.valid 533 // If replay is reported at load_s1, inst will be canceled (will not enter load_s2), 534 // in that case: 535 // * replay should not be reported twice 536 assert(!(RegNext(RegNext(io.feedbackFast.valid)) && io.feedbackSlow.valid)) 537 // * io.fastUop.valid should not be reported 538 assert(!RegNext(io.feedbackFast.valid && io.fastUop.valid)) 539 540 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 541 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 542 io.lsq.forward.sqIdxMask := sqIdxMaskReg 543 544 // // use s2_hit_way to select data received in s1 545 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 546 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 547 548 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 549 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 550 load_s1.io.in.valid && // valid laod request 551 !load_s1.io.fastUopKill && // not mmio or tlb miss 552 !io.lsq.forward.dataInvalidFast && // forward failed 553 !load_s1.io.needLdVioCheckRedo // load-load violation check: load paddr cam struct hazard 554 io.fastUop.bits := load_s1.io.out.bits.uop 555 556 XSDebug(load_s0.io.out.valid, 557 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 558 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 559 XSDebug(load_s1.io.out.valid, 560 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 561 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 562 563 // writeback to LSQ 564 // Current dcache use MSHR 565 // Load queue will be updated at s2 for both hit/miss int/fp load 566 io.lsq.loadIn.valid := load_s2.io.out.valid 567 io.lsq.loadIn.bits := load_s2.io.out.bits 568 569 // write to rob and writeback bus 570 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 571 572 // Int load, if hit, will be writebacked at s2 573 val hitLoadOut = Wire(Valid(new ExuOutput)) 574 hitLoadOut.valid := s2_wb_valid 575 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 576 hitLoadOut.bits.data := load_s2.io.out.bits.data 577 hitLoadOut.bits.redirectValid := false.B 578 hitLoadOut.bits.redirect := DontCare 579 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 580 hitLoadOut.bits.debug.isPerfCnt := false.B 581 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 582 hitLoadOut.bits.debug.vaddr := load_s2.io.out.bits.vaddr 583 hitLoadOut.bits.fflags := DontCare 584 585 load_s2.io.out.ready := true.B 586 587 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 588 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 589 590 io.lsq.ldout.ready := !hitLoadOut.valid 591 592 val lastValidData = RegEnable(io.ldout.bits.data, io.ldout.fire()) 593 val hitLoadAddrTriggerHitVec = Wire(Vec(3, Bool())) 594 val lqLoadAddrTriggerHitVec = io.lsq.trigger.lqLoadAddrTriggerHitVec 595 (0 until 3).map{i => { 596 val tdata2 = io.trigger(i).tdata2 597 val matchType = io.trigger(i).matchType 598 val tEnable = io.trigger(i).tEnable 599 hitLoadAddrTriggerHitVec(i) := TriggerCmp(io.ldout.bits.debug.vaddr, tdata2, matchType, tEnable) // this vaddr is 1 step after valid 600 io.trigger(i).addrHit := Mux(hitLoadOut.valid, hitLoadAddrTriggerHitVec(i), lqLoadAddrTriggerHitVec(i)) 601 io.trigger(i).lastDataHit := TriggerCmp(lastValidData, tdata2, matchType, tEnable) 602 }} 603 io.lsq.trigger.hitLoadAddrTriggerHitVec := hitLoadAddrTriggerHitVec 604 605 val perfEvents = Seq( 606 ("load_s0_in_fire ", load_s0.io.in.fire() ), 607 ("load_to_load_forward ", load_s0.io.loadFastMatch.orR && load_s0.io.in.fire() ), 608 ("stall_dcache ", load_s0.io.out.valid && load_s0.io.out.ready && !load_s0.io.dcacheReq.ready ), 609 ("addr_spec_success ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) === load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 610 ("addr_spec_failed ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) =/= load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 611 ("load_s1_in_fire ", load_s1.io.in.fire ), 612 ("load_s1_tlb_miss ", load_s1.io.in.fire && load_s1.io.dtlbResp.bits.miss ), 613 ("load_s2_in_fire ", load_s2.io.in.fire ), 614 ("load_s2_dcache_miss ", load_s2.io.in.fire && load_s2.io.dcacheResp.bits.miss ), 615 ("load_s2_replay ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit ), 616 ("load_s2_replay_tlb_miss ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && load_s2.io.in.bits.tlbMiss ), 617 ("load_s2_replay_cache ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && !load_s2.io.in.bits.tlbMiss && load_s2.io.dcacheResp.bits.miss), 618 ) 619 generatePerfEvent() 620 621 when(io.ldout.fire()){ 622 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 623 } 624} 625