1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan.ExceptionNO._ 24import xiangshan._ 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 28 29class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 30 val loadIn = ValidIO(new LsPipelineBundle) 31 val ldout = Flipped(DecoupledIO(new ExuOutput)) 32 val loadDataForwarded = Output(Bool()) 33 val needReplayFromRS = Output(Bool()) 34 val forward = new PipeLoadForwardQueryIO 35 val loadViolationQuery = new LoadViolationQueryIO 36} 37 38class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 39 // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 40 val data = UInt(XLEN.W) 41 val valid = Bool() 42} 43 44// Load Pipeline Stage 0 45// Generate addr, use addr to query DCache and DTLB 46class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParameters{ 47 val io = IO(new Bundle() { 48 val in = Flipped(Decoupled(new ExuInput)) 49 val out = Decoupled(new LsPipelineBundle) 50 val fastpath = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 51 val dtlbReq = DecoupledIO(new TlbReq) 52 val dcacheReq = DecoupledIO(new DCacheWordReq) 53 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 54 val isFirstIssue = Input(Bool()) 55 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 56 }) 57 require(LoadPipelineWidth == exuParameters.LduCnt) 58 59 val s0_uop = io.in.bits.uop 60 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 61 62 val s0_vaddr = WireInit(io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits)) 63 val s0_mask = WireInit(genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0))) 64 65 if (EnableLoadToLoadForward) { 66 // slow vaddr from non-load insts 67 val slowpath_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 68 val slowpath_mask = genWmask(slowpath_vaddr, s0_uop.ctrl.fuOpType(1,0)) 69 70 // fast vaddr from load insts 71 val fastpath_vaddrs = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 72 io.fastpath(i).data + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 73 }))) 74 val fastpath_masks = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 75 genWmask(fastpath_vaddrs(i), s0_uop.ctrl.fuOpType(1,0)) 76 }))) 77 val fastpath_vaddr = Mux1H(io.loadFastMatch, fastpath_vaddrs) 78 val fastpath_mask = Mux1H(io.loadFastMatch, fastpath_masks) 79 80 // select vaddr from 2 alus 81 s0_vaddr := Mux(io.loadFastMatch.orR, fastpath_vaddr, slowpath_vaddr) 82 s0_mask := Mux(io.loadFastMatch.orR, fastpath_mask, slowpath_mask) 83 XSPerfAccumulate("load_to_load_forward", io.loadFastMatch.orR && io.in.fire()) 84 } 85 86 val isSoftPrefetch = LSUOpType.isPrefetch(s0_uop.ctrl.fuOpType) 87 val isSoftPrefetchRead = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_r 88 val isSoftPrefetchWrite = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_w 89 90 // query DTLB 91 io.dtlbReq.valid := io.in.valid 92 io.dtlbReq.bits.vaddr := s0_vaddr 93 io.dtlbReq.bits.cmd := TlbCmd.read 94 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 95 io.dtlbReq.bits.robIdx := s0_uop.robIdx 96 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 97 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 98 99 // query DCache 100 io.dcacheReq.valid := io.in.valid 101 when (isSoftPrefetchRead) { 102 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFR 103 }.elsewhen (isSoftPrefetchWrite) { 104 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFW 105 }.otherwise { 106 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 107 } 108 io.dcacheReq.bits.addr := s0_vaddr 109 io.dcacheReq.bits.mask := s0_mask 110 io.dcacheReq.bits.data := DontCare 111 when(isSoftPrefetch) { 112 io.dcacheReq.bits.instrtype := SOFT_PREFETCH.U 113 }.otherwise { 114 io.dcacheReq.bits.instrtype := LOAD_SOURCE.U 115 } 116 117 // TODO: update cache meta 118 io.dcacheReq.bits.id := DontCare 119 120 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 121 "b00".U -> true.B, //b 122 "b01".U -> (s0_vaddr(0) === 0.U), //h 123 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 124 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 125 )) 126 127 io.out.valid := io.in.valid && io.dcacheReq.ready 128 129 io.out.bits := DontCare 130 io.out.bits.vaddr := s0_vaddr 131 io.out.bits.mask := s0_mask 132 io.out.bits.uop := s0_uop 133 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 134 io.out.bits.rsIdx := io.rsIdx 135 io.out.bits.isFirstIssue := io.isFirstIssue 136 io.out.bits.isSoftPrefetch := isSoftPrefetch 137 138 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 139 140 XSDebug(io.dcacheReq.fire(), 141 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 142 ) 143 XSPerfAccumulate("in_valid", io.in.valid) 144 XSPerfAccumulate("in_fire", io.in.fire) 145 XSPerfAccumulate("in_fire_first_issue", io.in.valid && io.isFirstIssue) 146 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 147 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 148 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 149 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 150 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 151 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 152} 153 154 155// Load Pipeline Stage 1 156// TLB resp (send paddr to dcache) 157class LoadUnit_S1(implicit p: Parameters) extends XSModule { 158 val io = IO(new Bundle() { 159 val in = Flipped(Decoupled(new LsPipelineBundle)) 160 val out = Decoupled(new LsPipelineBundle) 161 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 162 val dcachePAddr = Output(UInt(PAddrBits.W)) 163 val dcacheKill = Output(Bool()) 164 val fastUopKill = Output(Bool()) 165 val dcacheBankConflict = Input(Bool()) 166 val fullForwardFast = Output(Bool()) 167 val sbuffer = new LoadForwardQueryIO 168 val lsq = new PipeLoadForwardQueryIO 169 val loadViolationQueryReq = Decoupled(new LoadViolationQueryReq) 170 val rsFeedback = ValidIO(new RSFeedback) 171 val csrCtrl = Flipped(new CustomCSRCtrlIO) 172 val needLdVioCheckRedo = Output(Bool()) 173 }) 174 175 val s1_uop = io.in.bits.uop 176 val s1_paddr = io.dtlbResp.bits.paddr 177 // af & pf exception were modified below. 178 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, lduCfg).asUInt.orR 179 val s1_tlb_miss = io.dtlbResp.bits.miss 180 val s1_mask = io.in.bits.mask 181 val s1_bank_conflict = io.dcacheBankConflict 182 183 io.out.bits := io.in.bits // forwardXX field will be updated in s1 184 185 io.dtlbResp.ready := true.B 186 187 // TOOD: PMA check 188 io.dcachePAddr := s1_paddr 189 //io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 190 io.dcacheKill := s1_tlb_miss || s1_exception 191 io.fastUopKill := io.dtlbResp.bits.fast_miss || s1_exception 192 193 // load forward query datapath 194 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 195 io.sbuffer.vaddr := io.in.bits.vaddr 196 io.sbuffer.paddr := s1_paddr 197 io.sbuffer.uop := s1_uop 198 io.sbuffer.sqIdx := s1_uop.sqIdx 199 io.sbuffer.mask := s1_mask 200 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 201 202 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 203 io.lsq.vaddr := io.in.bits.vaddr 204 io.lsq.paddr := s1_paddr 205 io.lsq.uop := s1_uop 206 io.lsq.sqIdx := s1_uop.sqIdx 207 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 208 io.lsq.mask := s1_mask 209 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 210 211 // ld-ld violation query 212 io.loadViolationQueryReq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 213 io.loadViolationQueryReq.bits.paddr := s1_paddr 214 io.loadViolationQueryReq.bits.uop := s1_uop 215 216 // Generate forwardMaskFast to wake up insts earlier 217 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 218 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 219 220 // Generate feedback signal caused by: 221 // * dcache bank conflict 222 // * need redo ld-ld violation check 223 val needLdVioCheckRedo = io.loadViolationQueryReq.valid && 224 !io.loadViolationQueryReq.ready && 225 RegNext(io.csrCtrl.ldld_vio_check) 226 io.needLdVioCheckRedo := needLdVioCheckRedo 227 io.rsFeedback.valid := io.in.valid && (s1_bank_conflict || needLdVioCheckRedo) 228 io.rsFeedback.bits.hit := false.B // we have found s1_bank_conflict / re do ld-ld violation check 229 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 230 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 231 io.rsFeedback.bits.sourceType := Mux(s1_bank_conflict, RSFeedbackType.bankConflict, RSFeedbackType.ldVioCheckRedo) 232 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 233 234 // if replay is detected in load_s1, 235 // load inst will be canceled immediately 236 io.out.valid := io.in.valid && !io.rsFeedback.valid 237 io.out.bits.paddr := s1_paddr 238 io.out.bits.tlbMiss := s1_tlb_miss 239 240 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 241 // af & pf exception were modified 242 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 243 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 244 245 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 246 io.out.bits.rsIdx := io.in.bits.rsIdx 247 248 io.out.bits.isSoftPrefetch := io.in.bits.isSoftPrefetch 249 250 io.in.ready := !io.in.valid || io.out.ready 251 252 XSPerfAccumulate("in_valid", io.in.valid) 253 XSPerfAccumulate("in_fire", io.in.fire) 254 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 255 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 256 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 257 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 258} 259 260// Load Pipeline Stage 2 261// DCache resp 262class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 263 val io = IO(new Bundle() { 264 val in = Flipped(Decoupled(new LsPipelineBundle)) 265 val out = Decoupled(new LsPipelineBundle) 266 val rsFeedback = ValidIO(new RSFeedback) 267 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 268 val pmpResp = Flipped(new PMPRespBundle()) 269 val lsq = new LoadForwardQueryIO 270 val dataInvalidSqIdx = Input(UInt()) 271 val sbuffer = new LoadForwardQueryIO 272 val dataForwarded = Output(Bool()) 273 val needReplayFromRS = Output(Bool()) 274 val fullForward = Output(Bool()) 275 val fastpath = Output(new LoadToLoadIO) 276 val dcache_kill = Output(Bool()) 277 val loadViolationQueryResp = Flipped(Valid(new LoadViolationQueryResp)) 278 val csrCtrl = Flipped(new CustomCSRCtrlIO) 279 val sentFastUop = Input(Bool()) 280 }) 281 val isSoftPrefetch = io.in.bits.isSoftPrefetch 282 val excep = WireInit(io.in.bits.uop.cf.exceptionVec) 283 excep(loadAccessFault) := io.in.bits.uop.cf.exceptionVec(loadAccessFault) || io.pmpResp.ld 284 when (isSoftPrefetch) { 285 excep := 0.U.asTypeOf(excep.cloneType) 286 } 287 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, lduCfg).asUInt.orR 288 289 val actually_mmio = io.pmpResp.mmio 290 val s2_uop = io.in.bits.uop 291 val s2_mask = io.in.bits.mask 292 val s2_paddr = io.in.bits.paddr 293 val s2_tlb_miss = io.in.bits.tlbMiss 294 val s2_data_invalid = io.lsq.dataInvalid 295 val s2_mmio = !isSoftPrefetch && actually_mmio && !s2_exception 296 val s2_cache_miss = io.dcacheResp.bits.miss 297 val s2_cache_replay = io.dcacheResp.bits.replay 298 val s2_is_prefetch = io.in.bits.isSoftPrefetch 299 300 // val cnt = RegInit(127.U) 301 // cnt := cnt + io.in.valid.asUInt 302 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 303 304 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 305 // assert(!s2_forward_fail) 306 io.dcache_kill := false.B // move pmp resp kill to outside 307 io.dcacheResp.ready := true.B 308 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio || s2_is_prefetch) 309 assert(!(io.in.valid && (dcacheShouldResp && !io.dcacheResp.valid)), "DCache response got lost") 310 311 // merge forward result 312 // lsq has higher priority than sbuffer 313 val forwardMask = Wire(Vec(8, Bool())) 314 val forwardData = Wire(Vec(8, UInt(8.W))) 315 316 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 317 io.lsq := DontCare 318 io.sbuffer := DontCare 319 io.fullForward := fullForward 320 321 // generate XLEN/8 Muxs 322 for (i <- 0 until XLEN / 8) { 323 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 324 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 325 } 326 327 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 328 s2_uop.cf.pc, 329 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 330 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 331 ) 332 333 // data merge 334 val rdataVec = VecInit((0 until XLEN / 8).map(j => 335 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 336 val rdata = rdataVec.asUInt 337 val rdataSel = LookupTree(s2_paddr(2, 0), List( 338 "b000".U -> rdata(63, 0), 339 "b001".U -> rdata(63, 8), 340 "b010".U -> rdata(63, 16), 341 "b011".U -> rdata(63, 24), 342 "b100".U -> rdata(63, 32), 343 "b101".U -> rdata(63, 40), 344 "b110".U -> rdata(63, 48), 345 "b111".U -> rdata(63, 56) 346 )) 347 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 348 349 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 350 // Inst will be canceled in store queue / lsq, 351 // so we do not need to care about flush in load / store unit's out.valid 352 io.out.bits := io.in.bits 353 io.out.bits.data := rdataPartialLoad 354 // when exception occurs, set it to not miss and let it write back to rob (via int port) 355 if (EnableFastForward) { 356 io.out.bits.miss := s2_cache_miss && 357 !s2_exception && 358 !s2_forward_fail && 359 !fullForward && 360 !s2_is_prefetch 361 } else { 362 io.out.bits.miss := s2_cache_miss && 363 !s2_exception && 364 !s2_forward_fail && 365 !s2_is_prefetch 366 } 367 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 368 // if forward fail, replay this inst from fetch 369 val forwardFailReplay = s2_forward_fail && !s2_mmio 370 // if ld-ld violation is detected, replay from this inst from fetch 371 val ldldVioReplay = io.loadViolationQueryResp.valid && 372 io.loadViolationQueryResp.bits.have_violation && 373 RegNext(io.csrCtrl.ldld_vio_check) 374 io.out.bits.uop.ctrl.replayInst := forwardFailReplay || ldldVioReplay 375 io.out.bits.mmio := s2_mmio 376 io.out.bits.uop.ctrl.flushPipe := s2_mmio && io.sentFastUop 377 io.out.bits.uop.cf.exceptionVec := excep 378 379 // For timing reasons, sometimes we can not let 380 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 381 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 382 // and dcache query is no longer needed. 383 // Such inst will be writebacked from load queue. 384 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 385 // io.out.bits.forwardX will be send to lq 386 io.out.bits.forwardMask := forwardMask 387 // data retbrived from dcache is also included in io.out.bits.forwardData 388 io.out.bits.forwardData := rdataVec 389 390 io.in.ready := io.out.ready || !io.in.valid 391 392 // feedback tlb result to RS 393 io.rsFeedback.valid := io.in.valid 394 when (io.in.bits.isSoftPrefetch) { 395 io.rsFeedback.bits.hit := (!s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception)) 396 }.otherwise { 397 if (EnableFastForward) { 398 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 399 } else { 400 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) && !s2_data_invalid 401 } 402 } 403 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 404 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 405 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 406 Mux(s2_cache_replay, 407 RSFeedbackType.mshrFull, 408 RSFeedbackType.dataInvalid 409 ) 410 ) 411 io.rsFeedback.bits.dataInvalidSqIdx.value := io.dataInvalidSqIdx 412 io.rsFeedback.bits.dataInvalidSqIdx.flag := DontCare 413 414 // s2_cache_replay is quite slow to generate, send it separately to LQ 415 if (EnableFastForward) { 416 io.needReplayFromRS := s2_cache_replay && !fullForward 417 } else { 418 io.needReplayFromRS := s2_cache_replay 419 } 420 421 // fast load to load forward 422 io.fastpath.valid := io.in.valid // for debug only 423 io.fastpath.data := rdata // raw data 424 425 426 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 427 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 428 forwardData.asUInt, forwardMask.asUInt 429 ) 430 431 XSPerfAccumulate("in_valid", io.in.valid) 432 XSPerfAccumulate("in_fire", io.in.fire) 433 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 434 XSPerfAccumulate("dcache_miss", io.in.fire && s2_cache_miss) 435 XSPerfAccumulate("dcache_miss_first_issue", io.in.fire && s2_cache_miss && io.in.bits.isFirstIssue) 436 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 437 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 438 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 439 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 440 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 441 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 442 XSPerfAccumulate("replay_from_fetch_forward", io.out.valid && forwardFailReplay) 443 XSPerfAccumulate("replay_from_fetch_load_vio", io.out.valid && ldldVioReplay) 444} 445 446class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper with HasPerfEvents { 447 val io = IO(new Bundle() { 448 val ldin = Flipped(Decoupled(new ExuInput)) 449 val ldout = Decoupled(new ExuOutput) 450 val redirect = Flipped(ValidIO(new Redirect)) 451 val feedbackSlow = ValidIO(new RSFeedback) 452 val feedbackFast = ValidIO(new RSFeedback) 453 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 454 val isFirstIssue = Input(Bool()) 455 val dcache = new DCacheLoadIO 456 val sbuffer = new LoadForwardQueryIO 457 val lsq = new LoadToLsqIO 458 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 459 460 val tlb = new TlbRequestIO 461 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 462 463 val fastpathOut = Output(new LoadToLoadIO) 464 val fastpathIn = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 465 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 466 467 val csrCtrl = Flipped(new CustomCSRCtrlIO) 468 }) 469 470 val load_s0 = Module(new LoadUnit_S0) 471 val load_s1 = Module(new LoadUnit_S1) 472 val load_s2 = Module(new LoadUnit_S2) 473 474 load_s0.io.in <> io.ldin 475 load_s0.io.dtlbReq <> io.tlb.req 476 load_s0.io.dcacheReq <> io.dcache.req 477 load_s0.io.rsIdx := io.rsIdx 478 load_s0.io.isFirstIssue := io.isFirstIssue 479 load_s0.io.fastpath := io.fastpathIn 480 load_s0.io.loadFastMatch := io.loadFastMatch 481 482 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 483 484 load_s1.io.dtlbResp <> io.tlb.resp 485 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 486 io.dcache.s1_kill <> load_s1.io.dcacheKill 487 load_s1.io.sbuffer <> io.sbuffer 488 load_s1.io.lsq <> io.lsq.forward 489 load_s1.io.loadViolationQueryReq <> io.lsq.loadViolationQuery.req 490 load_s1.io.dcacheBankConflict <> io.dcache.s1_bank_conflict 491 load_s1.io.csrCtrl <> io.csrCtrl 492 493 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 494 495 io.dcache.s2_kill := load_s2.io.dcache_kill || (io.pmp.ld || io.pmp.mmio) // to kill mmio resp which are redirected 496 load_s2.io.dcacheResp <> io.dcache.resp 497 load_s2.io.pmpResp <> io.pmp 498 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 499 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 500 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 501 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 502 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 503 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 504 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 505 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 506 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 507 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 508 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 509 load_s2.io.fastpath <> io.fastpathOut 510 load_s2.io.dataInvalidSqIdx := io.lsq.forward.dataInvalidSqIdx // provide dataInvalidSqIdx to make wakeup faster 511 load_s2.io.loadViolationQueryResp <> io.lsq.loadViolationQuery.resp 512 load_s2.io.csrCtrl <> io.csrCtrl 513 load_s2.io.sentFastUop := RegEnable(io.fastUop.valid, load_s1.io.out.fire()) // RegNext is also ok 514 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 515 516 // feedback tlb miss / dcache miss queue full 517 io.feedbackSlow.bits := RegNext(load_s2.io.rsFeedback.bits) 518 io.feedbackSlow.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 519 520 // feedback bank conflict to rs 521 io.feedbackFast.bits := load_s1.io.rsFeedback.bits 522 io.feedbackFast.valid := load_s1.io.rsFeedback.valid 523 // If replay is reported at load_s1, inst will be canceled (will not enter load_s2), 524 // in that case: 525 // * replay should not be reported twice 526 assert(!(RegNext(RegNext(io.feedbackFast.valid)) && io.feedbackSlow.valid)) 527 // * io.fastUop.valid should not be reported 528 assert(!RegNext(io.feedbackFast.valid && io.fastUop.valid)) 529 530 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 531 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 532 io.lsq.forward.sqIdxMask := sqIdxMaskReg 533 534 // // use s2_hit_way to select data received in s1 535 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 536 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 537 538 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 539 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 540 load_s1.io.in.valid && // valid laod request 541 !load_s1.io.fastUopKill && // not mmio or tlb miss 542 !io.lsq.forward.dataInvalidFast && // forward failed 543 !load_s1.io.needLdVioCheckRedo // load-load violation check: load paddr cam struct hazard 544 io.fastUop.bits := load_s1.io.out.bits.uop 545 546 XSDebug(load_s0.io.out.valid, 547 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 548 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 549 XSDebug(load_s1.io.out.valid, 550 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 551 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 552 553 // writeback to LSQ 554 // Current dcache use MSHR 555 // Load queue will be updated at s2 for both hit/miss int/fp load 556 io.lsq.loadIn.valid := load_s2.io.out.valid 557 io.lsq.loadIn.bits := load_s2.io.out.bits 558 559 // write to rob and writeback bus 560 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 561 562 // Int load, if hit, will be writebacked at s2 563 val hitLoadOut = Wire(Valid(new ExuOutput)) 564 hitLoadOut.valid := s2_wb_valid 565 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 566 hitLoadOut.bits.data := load_s2.io.out.bits.data 567 hitLoadOut.bits.redirectValid := false.B 568 hitLoadOut.bits.redirect := DontCare 569 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 570 hitLoadOut.bits.debug.isPerfCnt := false.B 571 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 572 hitLoadOut.bits.debug.vaddr := load_s2.io.out.bits.vaddr 573 hitLoadOut.bits.fflags := DontCare 574 575 load_s2.io.out.ready := true.B 576 577 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 578 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 579 580 io.lsq.ldout.ready := !hitLoadOut.valid 581 582 val perfEvents = Seq( 583 ("load_s0_in_fire ", load_s0.io.in.fire() ), 584 ("load_to_load_forward ", load_s0.io.loadFastMatch.orR && load_s0.io.in.fire() ), 585 ("stall_dcache ", load_s0.io.out.valid && load_s0.io.out.ready && !load_s0.io.dcacheReq.ready ), 586 ("addr_spec_success ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) === load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 587 ("addr_spec_failed ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) =/= load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 588 ("load_s1_in_fire ", load_s1.io.in.fire ), 589 ("load_s1_tlb_miss ", load_s1.io.in.fire && load_s1.io.dtlbResp.bits.miss ), 590 ("load_s2_in_fire ", load_s2.io.in.fire ), 591 ("load_s2_dcache_miss ", load_s2.io.in.fire && load_s2.io.dcacheResp.bits.miss ), 592 ("load_s2_replay ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit ), 593 ("load_s2_replay_tlb_miss ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && load_s2.io.in.bits.tlbMiss ), 594 ("load_s2_replay_cache ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && !load_s2.io.in.bits.tlbMiss && load_s2.io.dcacheResp.bits.miss), 595 ) 596 generatePerfEvent() 597 598 when(io.ldout.fire()){ 599 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 600 } 601} 602