1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10 11class LoadToLsroqIO extends XSBundle { 12 val loadIn = ValidIO(new LsPipelineBundle) 13 val ldout = Flipped(DecoupledIO(new ExuOutput)) 14 val forward = new LoadForwardQueryIO 15} 16 17// Load Pipeline Stage 0 18// Generate addr, use addr to query DCache and DTLB 19class LoadUnit_S0 extends XSModule { 20 val io = IO(new Bundle() { 21 val in = Flipped(Decoupled(new ExuInput)) 22 val out = Decoupled(new LsPipelineBundle) 23 val redirect = Flipped(ValidIO(new Redirect)) 24 val dtlbReq = Valid(new TlbReq) 25 val dtlbResp = Flipped(Valid(new TlbResp)) 26 val tlbFeedback = ValidIO(new TlbFeedback) 27 val dcacheReq = DecoupledIO(new DCacheLoadReq) 28 }) 29 30 val s0_uop = io.in.bits.uop 31 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 32 val s0_paddr = io.dtlbResp.bits.paddr 33 val s0_tlb_miss = io.dtlbResp.bits.miss 34 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 35 36 // query DTLB 37 io.dtlbReq.valid := io.out.valid 38 io.dtlbReq.bits.vaddr := s0_vaddr 39 io.dtlbReq.bits.cmd := TlbCmd.read 40 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 41 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 42 io.dtlbReq.bits.debug.lsroqIdx := s0_uop.lsroqIdx 43 44 // feedback tlb result to RS 45 // Note: can be moved to s1 46 io.tlbFeedback.valid := io.out.valid 47 io.tlbFeedback.bits.hit := !s0_tlb_miss 48 io.tlbFeedback.bits.roqIdx := s0_uop.roqIdx 49 50 // query DCache 51 io.dcacheReq.valid := io.in.valid && !s0_uop.roqIdx.needFlush(io.redirect) 52 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 53 io.dcacheReq.bits.addr := s0_vaddr 54 io.dcacheReq.bits.mask := s0_mask 55 io.dcacheReq.bits.data := DontCare 56 57 // TODO: update cache meta 58 io.dcacheReq.bits.meta.id := DontCare 59 io.dcacheReq.bits.meta.vaddr := s0_vaddr 60 io.dcacheReq.bits.meta.paddr := DontCare 61 io.dcacheReq.bits.meta.uop := s0_uop 62 io.dcacheReq.bits.meta.mmio := false.B 63 io.dcacheReq.bits.meta.tlb_miss := false.B 64 io.dcacheReq.bits.meta.mask := s0_mask 65 io.dcacheReq.bits.meta.replay := false.B 66 67 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 68 "b00".U -> true.B, //b 69 "b01".U -> (s0_vaddr(0) === 0.U), //h 70 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 71 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 72 )) 73 74 io.out.valid := io.dcacheReq.fire() // dcache may not accept load request 75 io.out.bits := DontCare 76 io.out.bits.vaddr := s0_vaddr 77 io.out.bits.paddr := s0_paddr 78 io.out.bits.tlbMiss := io.dtlbResp.bits.miss 79 io.out.bits.mask := s0_mask 80 io.out.bits.uop := s0_uop 81 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 82 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 83 84 io.in.ready := io.out.fire() 85 86 XSDebug(io.dcacheReq.fire(), "[DCACHE LOAD REQ] pc %x vaddr %x paddr will be %x\n", 87 s0_uop.cf.pc, s0_vaddr, s0_paddr 88 ) 89} 90 91 92// Load Pipeline Stage 1 93// TLB resp (send paddr to dcache) 94class LoadUnit_S1 extends XSModule { 95 val io = IO(new Bundle() { 96 val in = Flipped(Decoupled(new LsPipelineBundle)) 97 val out = Decoupled(new LsPipelineBundle) 98 val redirect = Flipped(ValidIO(new Redirect)) 99 val forward = new LoadForwardQueryIO 100 // val s1_kill = Output(Bool()) 101 val s1_paddr = Output(UInt(PAddrBits.W)) 102 }) 103 104 val s1_uop = io.in.bits.uop 105 val s1_paddr = io.in.bits.paddr 106 val s1_tlb_miss = io.in.bits.tlbMiss 107 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 108 109 io.s1_paddr := s1_paddr 110 111 io.forward.valid := io.in.valid // && !s1_uop.needFlush(io.redirect) will cause comb. loop 112 io.forward.paddr := s1_paddr 113 io.forward.mask := io.in.bits.mask 114 io.forward.lsroqIdx := s1_uop.lsroqIdx 115 io.forward.sqIdx := s1_uop.sqIdx 116 io.forward.uop := s1_uop 117 io.forward.pc := s1_uop.cf.pc 118 119 io.out.valid := io.in.valid && !s1_uop.roqIdx.needFlush(io.redirect) 120 io.out.bits := io.in.bits 121 io.out.bits.paddr := s1_paddr 122 io.out.bits.mmio := s1_mmio 123 io.out.bits.tlbMiss := s1_tlb_miss 124 125 io.in.ready := io.out.ready || !io.in.valid 126 127} 128 129 130// Load Pipeline Stage 2 131// DCache resp 132class LoadUnit_S2 extends XSModule { 133 val io = IO(new Bundle() { 134 val in = Flipped(Decoupled(new LsPipelineBundle)) 135 val out = Decoupled(new LsPipelineBundle) 136 val redirect = Flipped(ValidIO(new Redirect)) 137 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 138 val sbuffer = new LoadForwardQueryIO 139 val lsroq = new LoadForwardQueryIO 140 }) 141 142 val s2_uop = io.in.bits.uop 143 val s2_mask = io.in.bits.mask 144 val s2_paddr = io.in.bits.paddr 145 val s2_cache_miss = io.dcacheResp.bits.miss 146 val s2_cache_nack = io.dcacheResp.bits.nack 147 148 // load forward query datapath 149 io.sbuffer.valid := io.in.valid 150 io.sbuffer.paddr := s2_paddr 151 io.sbuffer.uop := s2_uop 152 io.sbuffer.sqIdx := s2_uop.sqIdx 153 io.sbuffer.lsroqIdx := s2_uop.lsroqIdx 154 io.sbuffer.mask := s2_mask 155 io.sbuffer.pc := s2_uop.cf.pc // FIXME: remove it 156 157 io.lsroq.valid := io.in.valid 158 io.lsroq.paddr := s2_paddr 159 io.lsroq.uop := s2_uop 160 io.lsroq.sqIdx := s2_uop.sqIdx 161 io.lsroq.lsroqIdx := s2_uop.lsroqIdx 162 io.lsroq.mask := s2_mask 163 io.lsroq.pc := s2_uop.cf.pc // FIXME: remove it 164 165 io.dcacheResp.ready := true.B 166 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 167 168 val forwardMask = WireInit(io.sbuffer.forwardMask) 169 val forwardData = WireInit(io.sbuffer.forwardData) 170 // generate XLEN/8 Muxs 171 for (i <- 0 until XLEN / 8) { 172 when(io.lsroq.forwardMask(i)) { 173 forwardMask(i) := true.B 174 forwardData(i) := io.lsroq.forwardData(i) 175 } 176 } 177 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 178 179 // data merge 180 val rdata = VecInit((0 until XLEN / 8).map(j => 181 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 182 val rdataSel = LookupTree(s2_paddr(2, 0), List( 183 "b000".U -> rdata(63, 0), 184 "b001".U -> rdata(63, 8), 185 "b010".U -> rdata(63, 16), 186 "b011".U -> rdata(63, 24), 187 "b100".U -> rdata(63, 32), 188 "b101".U -> rdata(63, 40), 189 "b110".U -> rdata(63, 48), 190 "b111".U -> rdata(63, 56) 191 )) 192 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 193 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 194 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 195 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 196 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 197 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 198 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 199 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN) 200 )) 201 202 // TODO: ECC check 203 204 io.out.valid := io.in.valid // && !s2_uop.needFlush(io.redirect) will cause comb. loop 205 // Inst will be canceled in store queue / lsroq, 206 // so we do not need to care about flush in load / store unit's out.valid 207 io.out.bits := io.in.bits 208 io.out.bits.data := rdataPartialLoad 209 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 210 io.out.bits.mmio := io.in.bits.mmio 211 212 io.in.ready := io.out.ready || !io.in.valid 213 214 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b) + %x(%b)\n", 215 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 216 io.lsroq.forwardData.asUInt, io.lsroq.forwardMask.asUInt, 217 io.sbuffer.forwardData.asUInt, io.sbuffer.forwardMask.asUInt 218 ) 219 220} 221 222 223class LoadUnit extends XSModule { 224 val io = IO(new Bundle() { 225 val ldin = Flipped(Decoupled(new ExuInput)) 226 val ldout = Decoupled(new ExuOutput) 227 val redirect = Flipped(ValidIO(new Redirect)) 228 val tlbFeedback = ValidIO(new TlbFeedback) 229 val dcache = new DCacheLoadIO 230 val dtlb = new TlbRequestIO() 231 val sbuffer = new LoadForwardQueryIO 232 val lsroq = new LoadToLsroqIO 233 }) 234 235 val load_s0 = Module(new LoadUnit_S0) 236 val load_s1 = Module(new LoadUnit_S1) 237 val load_s2 = Module(new LoadUnit_S2) 238 239 load_s0.io.in <> io.ldin 240 load_s0.io.redirect <> io.redirect 241 load_s0.io.dtlbReq <> io.dtlb.req 242 load_s0.io.dtlbResp <> io.dtlb.resp 243 load_s0.io.dcacheReq <> io.dcache.req 244 load_s0.io.tlbFeedback <> io.tlbFeedback 245 246 PipelineConnect(load_s0.io.out, load_s1.io.in, load_s1.io.out.fire() || load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect), false.B) 247 248 io.dcache.s1_paddr := load_s1.io.out.bits.paddr 249 load_s1.io.redirect <> io.redirect 250 io.dcache.s1_kill := DontCare // FIXME 251// io.sbuffer <> load_s1.io.forward 252// io.lsroq.forward <> load_s1.io.forward 253 load_s1.io.forward <> DontCare // TODO: do we still need this? can we remove s1.io.forward? 254 255 PipelineConnect(load_s1.io.out, load_s2.io.in, load_s2.io.out.fire(), false.B) 256 257 load_s2.io.redirect <> io.redirect 258 load_s2.io.dcacheResp <> io.dcache.resp 259 io.sbuffer <> load_s2.io.sbuffer 260 io.lsroq.forward <> load_s2.io.lsroq 261// load_s2.io.sbuffer.forwardMask := io.sbuffer.forwardMask 262// load_s2.io.sbuffer.forwardData := io.sbuffer.forwardData 263// load_s2.io.lsroq.forwardMask := io.lsroq.forward.forwardMask 264// load_s2.io.lsroq.forwardData := io.lsroq.forward.forwardData 265 266 XSDebug(load_s0.io.out.valid, 267 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 268 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 269 XSDebug(load_s1.io.out.valid, 270 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 271 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 272 273 // writeback to LSROQ 274 // Current dcache use MSHR 275 io.lsroq.loadIn.valid := load_s2.io.out.valid 276 io.lsroq.loadIn.bits := load_s2.io.out.bits 277 278 val hitLoadOut = Wire(Valid(new ExuOutput)) 279 hitLoadOut.valid := load_s2.io.out.valid && !load_s2.io.out.bits.miss 280 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 281 hitLoadOut.bits.data := load_s2.io.out.bits.data 282 hitLoadOut.bits.redirectValid := false.B 283 hitLoadOut.bits.redirect := DontCare 284 hitLoadOut.bits.brUpdate := DontCare 285 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 286 287 // TODO: arbiter 288 // if hit, writeback result to CDB 289 // val ldout = Vec(2, Decoupled(new ExuOutput)) 290 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 291 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 292 // io.ldout <> cdbArb.io.out 293 // hitLoadOut <> cdbArb.io.in(0) 294 // io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut 295 load_s2.io.out.ready := true.B 296 io.lsroq.ldout.ready := !hitLoadOut.valid 297 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsroq.ldout.bits) 298 io.ldout.valid := hitLoadOut.valid || io.lsroq.ldout.valid 299 300 when(io.ldout.fire()){ 301 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 302 } 303} 304