1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10import xiangshan.backend.fu.fpu.boxF32ToF64 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val forward = new LoadForwardQueryIO 16} 17 18// Load Pipeline Stage 0 19// Generate addr, use addr to query DCache and DTLB 20class LoadUnit_S0 extends XSModule { 21 val io = IO(new Bundle() { 22 val in = Flipped(Decoupled(new ExuInput)) 23 val out = Decoupled(new LsPipelineBundle) 24 val redirect = Flipped(ValidIO(new Redirect)) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 27 val tlbFeedback = ValidIO(new TlbFeedback) 28 val dcacheReq = DecoupledIO(new DCacheLoadReq) 29 }) 30 31 val s0_uop = io.in.bits.uop 32 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 33 val s0_paddr = io.dtlbResp.bits.paddr 34 val s0_tlb_miss = io.dtlbResp.bits.miss 35 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 36 37 // query DTLB 38 io.dtlbReq.valid := io.out.valid 39 io.dtlbReq.bits.vaddr := s0_vaddr 40 io.dtlbReq.bits.cmd := TlbCmd.read 41 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 42 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 43 io.dtlbResp.ready := io.out.ready // TODO: check it: io.out.fire()? 44 45 // feedback tlb result to RS 46 // Note: can be moved to s1 47 io.tlbFeedback.valid := io.out.valid 48 io.tlbFeedback.bits.hit := !s0_tlb_miss 49 io.tlbFeedback.bits.roqIdx := s0_uop.roqIdx 50 51 // query DCache 52 io.dcacheReq.valid := io.in.valid && !s0_uop.roqIdx.needFlush(io.redirect) 53 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 54 io.dcacheReq.bits.addr := s0_vaddr 55 io.dcacheReq.bits.mask := s0_mask 56 io.dcacheReq.bits.data := DontCare 57 58 // TODO: update cache meta 59 io.dcacheReq.bits.meta.id := DontCare 60 io.dcacheReq.bits.meta.vaddr := s0_vaddr 61 io.dcacheReq.bits.meta.paddr := DontCare 62 io.dcacheReq.bits.meta.uop := s0_uop 63 io.dcacheReq.bits.meta.mmio := false.B 64 io.dcacheReq.bits.meta.tlb_miss := false.B 65 io.dcacheReq.bits.meta.mask := s0_mask 66 io.dcacheReq.bits.meta.replay := false.B 67 68 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 69 "b00".U -> true.B, //b 70 "b01".U -> (s0_vaddr(0) === 0.U), //h 71 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 72 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 73 )) 74 75 io.out.valid := io.dcacheReq.fire() // dcache may not accept load request 76 io.out.bits := DontCare 77 io.out.bits.vaddr := s0_vaddr 78 io.out.bits.paddr := s0_paddr 79 io.out.bits.tlbMiss := io.dtlbResp.bits.miss 80 io.out.bits.mask := s0_mask 81 io.out.bits.uop := s0_uop 82 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 83 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 84 85 io.in.ready := io.out.fire() 86 87 XSDebug(io.dcacheReq.fire(), "[DCACHE LOAD REQ] pc %x vaddr %x paddr will be %x\n", 88 s0_uop.cf.pc, s0_vaddr, s0_paddr 89 ) 90} 91 92 93// Load Pipeline Stage 1 94// TLB resp (send paddr to dcache) 95class LoadUnit_S1 extends XSModule { 96 val io = IO(new Bundle() { 97 val in = Flipped(Decoupled(new LsPipelineBundle)) 98 val out = Decoupled(new LsPipelineBundle) 99 val redirect = Flipped(ValidIO(new Redirect)) 100 val s1_paddr = Output(UInt(PAddrBits.W)) 101 val sbuffer = new LoadForwardQueryIO 102 val lsq = new LoadForwardQueryIO 103 }) 104 105 val s1_uop = io.in.bits.uop 106 val s1_paddr = io.in.bits.paddr 107 val s1_tlb_miss = io.in.bits.tlbMiss 108 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) && !io.out.bits.uop.cf.exceptionVec.asUInt.orR 109 val s1_mask = io.in.bits.mask 110 111 io.out.bits := io.in.bits // forwardXX field will be updated in s1 112 io.s1_paddr := s1_paddr 113 114 // load forward query datapath 115 io.sbuffer.valid := io.in.valid 116 io.sbuffer.paddr := s1_paddr 117 io.sbuffer.uop := s1_uop 118 io.sbuffer.sqIdx := s1_uop.sqIdx 119 io.sbuffer.mask := s1_mask 120 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 121 122 io.lsq.valid := io.in.valid 123 io.lsq.paddr := s1_paddr 124 io.lsq.uop := s1_uop 125 io.lsq.sqIdx := s1_uop.sqIdx 126 io.lsq.mask := s1_mask 127 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 128 129 io.out.bits.forwardMask := io.sbuffer.forwardMask 130 io.out.bits.forwardData := io.sbuffer.forwardData 131 // generate XLEN/8 Muxs 132 for (i <- 0 until XLEN / 8) { 133 when(io.lsq.forwardMask(i)) { 134 io.out.bits.forwardMask(i) := true.B 135 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 136 } 137 } 138 139 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 140 s1_uop.cf.pc, 141 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 142 io.sbuffer.forwardData.asUInt, io.sbuffer.forwardMask.asUInt 143 ) 144 145 io.out.valid := io.in.valid && !s1_tlb_miss && !s1_uop.roqIdx.needFlush(io.redirect) 146 io.out.bits.paddr := s1_paddr 147 io.out.bits.mmio := s1_mmio 148 io.out.bits.tlbMiss := s1_tlb_miss 149 150 io.in.ready := io.out.ready || !io.in.valid 151 152} 153 154 155// Load Pipeline Stage 2 156// DCache resp 157class LoadUnit_S2 extends XSModule { 158 val io = IO(new Bundle() { 159 val in = Flipped(Decoupled(new LsPipelineBundle)) 160 val out = Decoupled(new LsPipelineBundle) 161 val redirect = Flipped(ValidIO(new Redirect)) 162 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 163 }) 164 165 val s2_uop = io.in.bits.uop 166 val s2_mask = io.in.bits.mask 167 val s2_paddr = io.in.bits.paddr 168 val s2_cache_miss = io.dcacheResp.bits.miss 169 val s2_cache_nack = io.dcacheResp.bits.nack 170 171 172 io.dcacheResp.ready := true.B 173 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 174 175 val forwardMask = io.in.bits.forwardMask 176 val forwardData = io.in.bits.forwardData 177 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 178 179 // data merge 180 val rdata = VecInit((0 until XLEN / 8).map(j => 181 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 182 val rdataSel = LookupTree(s2_paddr(2, 0), List( 183 "b000".U -> rdata(63, 0), 184 "b001".U -> rdata(63, 8), 185 "b010".U -> rdata(63, 16), 186 "b011".U -> rdata(63, 24), 187 "b100".U -> rdata(63, 32), 188 "b101".U -> rdata(63, 40), 189 "b110".U -> rdata(63, 48), 190 "b111".U -> rdata(63, 56) 191 )) 192 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 193 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 194 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 195 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 196 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 197 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 198 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 199 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN), 200 LSUOpType.flw -> boxF32ToF64(rdataSel(31, 0)) 201 )) 202 203 // TODO: ECC check 204 205 io.out.valid := io.in.valid // && !s2_uop.needFlush(io.redirect) will cause comb. loop 206 // Inst will be canceled in store queue / lsq, 207 // so we do not need to care about flush in load / store unit's out.valid 208 io.out.bits := io.in.bits 209 io.out.bits.data := rdataPartialLoad 210 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 211 io.out.bits.mmio := io.in.bits.mmio 212 213 io.in.ready := io.out.ready || !io.in.valid 214 215 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 216 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 217 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 218 ) 219 220} 221 222 223class LoadUnit extends XSModule { 224 val io = IO(new Bundle() { 225 val ldin = Flipped(Decoupled(new ExuInput)) 226 val ldout = Decoupled(new ExuOutput) 227 val redirect = Flipped(ValidIO(new Redirect)) 228 val tlbFeedback = ValidIO(new TlbFeedback) 229 val dcache = new DCacheLoadIO 230 val dtlb = new TlbRequestIO() 231 val sbuffer = new LoadForwardQueryIO 232 val lsq = new LoadToLsqIO 233 }) 234 235 val load_s0 = Module(new LoadUnit_S0) 236 val load_s1 = Module(new LoadUnit_S1) 237 val load_s2 = Module(new LoadUnit_S2) 238 239 load_s0.io.in <> io.ldin 240 load_s0.io.redirect <> io.redirect 241 load_s0.io.dtlbReq <> io.dtlb.req 242 load_s0.io.dtlbResp <> io.dtlb.resp 243 load_s0.io.dcacheReq <> io.dcache.req 244 load_s0.io.tlbFeedback <> io.tlbFeedback 245 246 PipelineConnect(load_s0.io.out, load_s1.io.in, load_s1.io.out.fire() || load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect), false.B) 247 248 io.dcache.s1_paddr := load_s1.io.out.bits.paddr 249 load_s1.io.redirect <> io.redirect 250 io.dcache.s1_kill := DontCare // FIXME 251 io.sbuffer <> load_s1.io.sbuffer 252 io.lsq.forward <> load_s1.io.lsq 253 254 PipelineConnect(load_s1.io.out, load_s2.io.in, load_s2.io.out.fire() || load_s1.io.out.bits.tlbMiss, false.B) 255 256 load_s2.io.redirect <> io.redirect 257 load_s2.io.dcacheResp <> io.dcache.resp 258 259 XSDebug(load_s0.io.out.valid, 260 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 261 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 262 XSDebug(load_s1.io.out.valid, 263 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 264 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 265 266 // writeback to LSQ 267 // Current dcache use MSHR 268 io.lsq.loadIn.valid := load_s2.io.out.valid 269 io.lsq.loadIn.bits := load_s2.io.out.bits 270 271 val hitLoadOut = Wire(Valid(new ExuOutput)) 272 hitLoadOut.valid := load_s2.io.out.valid && (!load_s2.io.out.bits.miss || load_s2.io.out.bits.uop.cf.exceptionVec.asUInt.orR) 273 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 274 hitLoadOut.bits.data := load_s2.io.out.bits.data 275 hitLoadOut.bits.redirectValid := false.B 276 hitLoadOut.bits.redirect := DontCare 277 hitLoadOut.bits.brUpdate := DontCare 278 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 279 hitLoadOut.bits.fflags := DontCare 280 281 // TODO: arbiter 282 // if hit, writeback result to CDB 283 // val ldout = Vec(2, Decoupled(new ExuOutput)) 284 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 285 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 286 // io.ldout <> cdbArb.io.out 287 // hitLoadOut <> cdbArb.io.in(0) 288 // io.lsq.ldout <> cdbArb.io.in(1) // missLoadOut 289 load_s2.io.out.ready := true.B 290 io.lsq.ldout.ready := !hitLoadOut.valid 291 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 292 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 293 294 when(io.ldout.fire()){ 295 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 296 } 297}