1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val forward = new LoadForwardQueryIO 17} 18 19// Load Pipeline Stage 0 20// Generate addr, use addr to query DCache and DTLB 21class LoadUnit_S0 extends XSModule { 22 val io = IO(new Bundle() { 23 val in = Flipped(Decoupled(new ExuInput)) 24 val out = Decoupled(new LsPipelineBundle) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dcacheReq = DecoupledIO(new DCacheWordReq) 27 }) 28 29 val s0_uop = io.in.bits.uop 30 val s0_vaddr = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 31 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 32 33 // query DTLB 34 io.dtlbReq.valid := io.in.valid 35 io.dtlbReq.bits.vaddr := s0_vaddr 36 io.dtlbReq.bits.cmd := TlbCmd.read 37 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 38 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 39 40 // query DCache 41 io.dcacheReq.valid := io.in.valid 42 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 43 io.dcacheReq.bits.addr := s0_vaddr 44 io.dcacheReq.bits.mask := s0_mask 45 io.dcacheReq.bits.data := DontCare 46 47 // TODO: update cache meta 48 io.dcacheReq.bits.meta.id := DontCare 49 io.dcacheReq.bits.meta.vaddr := s0_vaddr 50 io.dcacheReq.bits.meta.paddr := DontCare 51 io.dcacheReq.bits.meta.uop := s0_uop 52 io.dcacheReq.bits.meta.mmio := false.B 53 io.dcacheReq.bits.meta.tlb_miss := false.B 54 io.dcacheReq.bits.meta.mask := s0_mask 55 io.dcacheReq.bits.meta.replay := false.B 56 57 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 58 "b00".U -> true.B, //b 59 "b01".U -> (s0_vaddr(0) === 0.U), //h 60 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 61 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 62 )) 63 64 io.out.valid := io.in.valid && io.dcacheReq.ready 65 66 io.out.bits := DontCare 67 io.out.bits.vaddr := s0_vaddr 68 io.out.bits.mask := s0_mask 69 io.out.bits.uop := s0_uop 70 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 71 72 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 73 74 XSDebug(io.dcacheReq.fire(), 75 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 76 ) 77} 78 79 80// Load Pipeline Stage 1 81// TLB resp (send paddr to dcache) 82class LoadUnit_S1 extends XSModule { 83 val io = IO(new Bundle() { 84 val in = Flipped(Decoupled(new LsPipelineBundle)) 85 val out = Decoupled(new LsPipelineBundle) 86 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 87 val dcachePAddr = Output(UInt(PAddrBits.W)) 88 val dcacheKill = Output(Bool()) 89 val sbuffer = new LoadForwardQueryIO 90 val lsq = new LoadForwardQueryIO 91 }) 92 93 val s1_uop = io.in.bits.uop 94 val s1_paddr = io.dtlbResp.bits.paddr 95 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 96 val s1_tlb_miss = io.dtlbResp.bits.miss 97 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 98 val s1_mask = io.in.bits.mask 99 100 io.out.bits := io.in.bits // forwardXX field will be updated in s1 101 102 io.dtlbResp.ready := true.B 103 104 // TOOD: PMA check 105 io.dcachePAddr := s1_paddr 106 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 107 108 // load forward query datapath 109 io.sbuffer.valid := io.in.valid 110 io.sbuffer.paddr := s1_paddr 111 io.sbuffer.uop := s1_uop 112 io.sbuffer.sqIdx := s1_uop.sqIdx 113 io.sbuffer.mask := s1_mask 114 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 115 116 io.lsq.valid := io.in.valid 117 io.lsq.paddr := s1_paddr 118 io.lsq.uop := s1_uop 119 io.lsq.sqIdx := s1_uop.sqIdx 120 io.lsq.mask := s1_mask 121 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 122 123 io.out.valid := io.in.valid// && !s1_tlb_miss 124 io.out.bits.paddr := s1_paddr 125 io.out.bits.mmio := s1_mmio && !s1_exception 126 io.out.bits.tlbMiss := s1_tlb_miss 127 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 128 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 129 130 io.in.ready := !io.in.valid || io.out.ready 131 132} 133 134 135// Load Pipeline Stage 2 136// DCache resp 137class LoadUnit_S2 extends XSModule with HasLoadHelper { 138 val io = IO(new Bundle() { 139 val in = Flipped(Decoupled(new LsPipelineBundle)) 140 val out = Decoupled(new LsPipelineBundle) 141 val tlbFeedback = ValidIO(new TlbFeedback) 142 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 143 val lsq = new LoadForwardQueryIO 144 val sbuffer = new LoadForwardQueryIO 145 val dataForwarded = Output(Bool()) 146 }) 147 148 val s2_uop = io.in.bits.uop 149 val s2_mask = io.in.bits.mask 150 val s2_paddr = io.in.bits.paddr 151 val s2_tlb_miss = io.in.bits.tlbMiss 152 val s2_mmio = io.in.bits.mmio 153 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 154 val s2_cache_miss = io.dcacheResp.bits.miss 155 val s2_cache_replay = io.dcacheResp.bits.replay 156 157 io.dcacheResp.ready := true.B 158 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 159 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 160 161 // feedback tlb result to RS 162 io.tlbFeedback.valid := io.in.valid 163 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 164 io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx 165 166 val forwardMask = io.out.bits.forwardMask 167 val forwardData = io.out.bits.forwardData 168 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 169 170 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 171 s2_uop.cf.pc, 172 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 173 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 174 ) 175 176 // data merge 177 val rdata = VecInit((0 until XLEN / 8).map(j => 178 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 179 val rdataSel = LookupTree(s2_paddr(2, 0), List( 180 "b000".U -> rdata(63, 0), 181 "b001".U -> rdata(63, 8), 182 "b010".U -> rdata(63, 16), 183 "b011".U -> rdata(63, 24), 184 "b100".U -> rdata(63, 32), 185 "b101".U -> rdata(63, 40), 186 "b110".U -> rdata(63, 48), 187 "b111".U -> rdata(63, 56) 188 )) 189 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 190 191 // TODO: ECC check 192 193 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 194 // Inst will be canceled in store queue / lsq, 195 // so we do not need to care about flush in load / store unit's out.valid 196 io.out.bits := io.in.bits 197 io.out.bits.data := rdataPartialLoad 198 // when exception occurs, set it to not miss and let it write back to roq (via int port) 199 io.out.bits.miss := s2_cache_miss && !s2_exception 200 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 201 io.out.bits.mmio := s2_mmio 202 203 // For timing reasons, we can not let 204 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 205 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 206 // and dcache query is no longer needed. 207 // Such inst will be writebacked from load queue. 208 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 209 210 io.in.ready := io.out.ready || !io.in.valid 211 212 // merge forward result 213 // lsq has higher priority than sbuffer 214 io.lsq := DontCare 215 io.sbuffer := DontCare 216 // generate XLEN/8 Muxs 217 for (i <- 0 until XLEN / 8) { 218 when (io.sbuffer.forwardMask(i)) { 219 io.out.bits.forwardMask(i) := true.B 220 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 221 } 222 when (io.lsq.forwardMask(i)) { 223 io.out.bits.forwardMask(i) := true.B 224 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 225 } 226 } 227 228 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 229 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 230 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 231 ) 232} 233 234class LoadUnit extends XSModule with HasLoadHelper { 235 val io = IO(new Bundle() { 236 val ldin = Flipped(Decoupled(new ExuInput)) 237 val ldout = Decoupled(new ExuOutput) 238 val fpout = Decoupled(new ExuOutput) 239 val redirect = Flipped(ValidIO(new Redirect)) 240 val tlbFeedback = ValidIO(new TlbFeedback) 241 val dcache = new DCacheLoadIO 242 val dtlb = new TlbRequestIO() 243 val sbuffer = new LoadForwardQueryIO 244 val lsq = new LoadToLsqIO 245 }) 246 247 val load_s0 = Module(new LoadUnit_S0) 248 val load_s1 = Module(new LoadUnit_S1) 249 val load_s2 = Module(new LoadUnit_S2) 250 251 load_s0.io.in <> io.ldin 252 load_s0.io.dtlbReq <> io.dtlb.req 253 load_s0.io.dcacheReq <> io.dcache.req 254 255 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 256 257 load_s1.io.dtlbResp <> io.dtlb.resp 258 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 259 io.dcache.s1_kill <> load_s1.io.dcacheKill 260 load_s1.io.sbuffer <> io.sbuffer 261 load_s1.io.lsq <> io.lsq.forward 262 263 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 264 265 load_s2.io.tlbFeedback <> io.tlbFeedback 266 load_s2.io.dcacheResp <> io.dcache.resp 267 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 268 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 269 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 270 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 271 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 272 273 XSDebug(load_s0.io.out.valid, 274 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 275 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 276 XSDebug(load_s1.io.out.valid, 277 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 278 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 279 280 // writeback to LSQ 281 // Current dcache use MSHR 282 // Load queue will be updated at s2 for both hit/miss int/fp load 283 io.lsq.loadIn.valid := load_s2.io.out.valid 284 io.lsq.loadIn.bits := load_s2.io.out.bits 285 286 // write to rob and writeback bus 287 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 288 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 289 290 // Int load, if hit, will be writebacked at s2 291 val intHitLoadOut = Wire(Valid(new ExuOutput)) 292 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 293 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 294 intHitLoadOut.bits.data := load_s2.io.out.bits.data 295 intHitLoadOut.bits.redirectValid := false.B 296 intHitLoadOut.bits.redirect := DontCare 297 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 298 intHitLoadOut.bits.debug.isPerfCnt := false.B 299 intHitLoadOut.bits.fflags := DontCare 300 301 load_s2.io.out.ready := true.B 302 303 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 304 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 305 306 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 307 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 308 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 309 fpHitLoadOut.bits := intHitLoadOut.bits 310 311 val fpLoadOut = Wire(Valid(new ExuOutput)) 312 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 313 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 314 315 val fpLoadOutReg = RegNext(fpLoadOut) 316 io.fpout.bits := fpLoadOutReg.bits 317 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 318 io.fpout.valid := RegNext(fpLoadOut.valid) 319 320 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 321 322 when(io.ldout.fire()){ 323 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 324 } 325 326 when(io.fpout.fire()){ 327 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 328 } 329} 330