1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.rob.{DebugLsInfoBundle, LsTopdownInfo, RobPtr} 28import xiangshan.cache._ 29import xiangshan.cache.wpu.ReplayCarry 30import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 31import xiangshan.mem.mdp._ 32 33class LoadToLsqReplayIO(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 34 // mshr refill index 35 val mshr_id = UInt(log2Up(cfg.nMissEntries).W) 36 // get full data from store queue and sbuffer 37 val full_fwd = Bool() 38 // wait for data from store inst's store queue index 39 val data_inv_sq_idx = new SqPtr 40 // wait for address from store queue index 41 val addr_inv_sq_idx = new SqPtr 42 // replay carry 43 val rep_carry = new ReplayCarry(nWays) 44 // data in last beat 45 val last_beat = Bool() 46 // replay cause 47 val cause = Vec(LoadReplayCauses.allCauses, Bool()) 48 // performance debug information 49 val debug = new PerfDebugInfo 50 51 // alias 52 def mem_amb = cause(LoadReplayCauses.C_MA) 53 def tlb_miss = cause(LoadReplayCauses.C_TM) 54 def fwd_fail = cause(LoadReplayCauses.C_FF) 55 def dcache_rep = cause(LoadReplayCauses.C_DR) 56 def dcache_miss = cause(LoadReplayCauses.C_DM) 57 def wpu_fail = cause(LoadReplayCauses.C_WF) 58 def bank_conflict = cause(LoadReplayCauses.C_BC) 59 def rar_nack = cause(LoadReplayCauses.C_RAR) 60 def raw_nack = cause(LoadReplayCauses.C_RAW) 61 def nuke = cause(LoadReplayCauses.C_NK) 62 def need_rep = cause.asUInt.orR 63} 64 65 66class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 67 val ldin = DecoupledIO(new LqWriteBundle) 68 val uncache = Flipped(DecoupledIO(new ExuOutput)) 69 val ld_raw_data = Input(new LoadDataFromLQBundle) 70 val forward = new PipeLoadForwardQueryIO 71 val stld_nuke_query = new LoadNukeQueryIO 72 val ldld_nuke_query = new LoadNukeQueryIO 73 val trigger = Flipped(new LqTriggerIO) 74} 75 76class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 77 val valid = Bool() 78 val data = UInt(XLEN.W) // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 79 val dly_ld_err = Bool() 80} 81 82class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 83 val tdata2 = Input(UInt(64.W)) 84 val matchType = Input(UInt(2.W)) 85 val tEnable = Input(Bool()) // timing is calculated before this 86 val addrHit = Output(Bool()) 87 val lastDataHit = Output(Bool()) 88} 89 90class LoadUnit(implicit p: Parameters) extends XSModule 91 with HasLoadHelper 92 with HasPerfEvents 93 with HasDCacheParameters 94 with HasCircularQueuePtrHelper 95{ 96 val io = IO(new Bundle() { 97 // control 98 val redirect = Flipped(ValidIO(new Redirect)) 99 val csrCtrl = Flipped(new CustomCSRCtrlIO) 100 101 // int issue path 102 val ldin = Flipped(Decoupled(new ExuInput)) 103 val ldout = Decoupled(new ExuOutput) 104 val rsIdx = Input(UInt()) 105 val isFirstIssue = Input(Bool()) 106 107 // data path 108 val tlb = new TlbRequestIO(2) 109 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 110 val dcache = new DCacheLoadIO 111 val sbuffer = new LoadForwardQueryIO 112 val lsq = new LoadToLsqIO 113 val tl_d_channel = Input(new DcacheToLduForwardIO) 114 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 115 val refill = Flipped(ValidIO(new Refill)) 116 val l2_hint = Input(Valid(new L2ToL1Hint)) 117 118 // fast wakeup 119 val fast_uop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1, send to RS in load_s2 120 121 // trigger 122 val trigger = Vec(3, new LoadUnitTriggerIO) 123 124 // prefetch 125 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info 126 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) // hardware prefetch to l1 cache req 127 128 // load to load fast path 129 val l2l_fwd_in = Input(new LoadToLoadIO) 130 val l2l_fwd_out = Output(new LoadToLoadIO) 131 132 val ld_fast_match = Input(Bool()) 133 val ld_fast_fuOpType = Input(UInt()) 134 val ld_fast_imm = Input(UInt(12.W)) 135 136 // rs feedback 137 val feedback_fast = ValidIO(new RSFeedback) // stage 2 138 val feedback_slow = ValidIO(new RSFeedback) // stage 3 139 140 // load ecc error 141 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 142 143 // schedule error query 144 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 145 146 // queue-based replay 147 val replay = Flipped(Decoupled(new LsPipelineBundle)) 148 val lq_rep_full = Input(Bool()) 149 150 // misc 151 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 152 153 // Load fast replay path 154 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 155 val fast_rep_out = Decoupled(new LqWriteBundle) 156 157 // perf 158 val debug_ls = Output(new DebugLsInfoBundle) 159 val lsTopdownInfo = Output(new LsTopdownInfo) 160 }) 161 162 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 163 164 // Pipeline 165 // -------------------------------------------------------------------------------- 166 // stage 0 167 // -------------------------------------------------------------------------------- 168 // generate addr, use addr to query DCache and DTLB 169 val s0_valid = Wire(Bool()) 170 val s0_kill = Wire(Bool()) 171 val s0_vaddr = Wire(UInt(VAddrBits.W)) 172 val s0_mask = Wire(UInt((VLEN/8).W)) 173 val s0_uop = Wire(new MicroOp) 174 val s0_has_rob_entry = Wire(Bool()) 175 val s0_rsIdx = Wire(UInt(log2Up(IssQueSize).W)) 176 val s0_mshrid = Wire(UInt()) 177 val s0_try_l2l = Wire(Bool()) 178 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 179 val s0_isFirstIssue = Wire(Bool()) 180 val s0_fast_rep = Wire(Bool()) 181 val s0_ld_rep = Wire(Bool()) 182 val s0_l2l_fwd = Wire(Bool()) 183 val s0_sched_idx = Wire(UInt()) 184 val s0_can_go = s1_ready 185 val s0_fire = s0_valid && s0_can_go 186 val s0_out = Wire(new LqWriteBundle) 187 188 // load flow select/gen 189 // src0: super load replayed by LSQ (cache miss replay) (io.replay) 190 // src1: fast load replay (io.fast_rep_in) 191 // src2: load replayed by LSQ (io.replay) 192 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 193 // src4: int read / software prefetch first issue from RS (io.in) 194 // src5: vec read first issue from RS (TODO) 195 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 196 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 197 // priority: high to low 198 val s0_rep_stall = io.ldin.valid && isAfter(io.replay.bits.uop.robIdx, io.ldin.bits.uop.robIdx) 199 val s0_super_ld_rep_valid = io.replay.valid && io.replay.bits.forward_tlDchannel 200 val s0_ld_fast_rep_valid = io.fast_rep_in.valid 201 val s0_ld_rep_valid = io.replay.valid && !io.replay.bits.forward_tlDchannel && !s0_rep_stall 202 val s0_high_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence > 0.U 203 val s0_int_iss_valid = io.ldin.valid // int flow first issue or software prefetch 204 val s0_vec_iss_valid = WireInit(false.B) // TODO 205 val s0_l2l_fwd_valid = io.l2l_fwd_in.valid && io.ld_fast_match 206 val s0_low_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence === 0.U 207 dontTouch(s0_super_ld_rep_valid) 208 dontTouch(s0_ld_fast_rep_valid) 209 dontTouch(s0_ld_rep_valid) 210 dontTouch(s0_high_conf_prf_valid) 211 dontTouch(s0_int_iss_valid) 212 dontTouch(s0_vec_iss_valid) 213 dontTouch(s0_l2l_fwd_valid) 214 dontTouch(s0_low_conf_prf_valid) 215 216 // load flow source ready 217 val s0_super_ld_rep_ready = WireInit(true.B) 218 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 219 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 220 !s0_ld_fast_rep_valid 221 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 222 !s0_ld_fast_rep_valid && 223 !s0_ld_rep_valid 224 225 val s0_int_iss_ready = !s0_super_ld_rep_valid && 226 !s0_ld_fast_rep_valid && 227 !s0_ld_rep_valid && 228 !s0_high_conf_prf_valid 229 230 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 231 !s0_ld_fast_rep_valid && 232 !s0_ld_rep_valid && 233 !s0_high_conf_prf_valid && 234 !s0_int_iss_valid 235 236 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 237 !s0_ld_fast_rep_valid && 238 !s0_ld_rep_valid && 239 !s0_high_conf_prf_valid && 240 !s0_int_iss_valid && 241 !s0_vec_iss_valid 242 243 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 244 !s0_ld_fast_rep_valid && 245 !s0_ld_rep_valid && 246 !s0_high_conf_prf_valid && 247 !s0_int_iss_valid && 248 !s0_vec_iss_valid && 249 !s0_l2l_fwd_valid 250 dontTouch(s0_super_ld_rep_ready) 251 dontTouch(s0_ld_fast_rep_ready) 252 dontTouch(s0_ld_rep_ready) 253 dontTouch(s0_high_conf_prf_ready) 254 dontTouch(s0_int_iss_ready) 255 dontTouch(s0_vec_iss_ready) 256 dontTouch(s0_l2l_fwd_ready) 257 dontTouch(s0_low_conf_prf_ready) 258 259 // load flow source select (OH) 260 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 261 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 262 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 263 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 264 s0_low_conf_prf_ready && s0_low_conf_prf_valid 265 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 266 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 267 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 268 assert(!s0_vec_iss_select) // to be added 269 dontTouch(s0_super_ld_rep_select) 270 dontTouch(s0_ld_fast_rep_select) 271 dontTouch(s0_ld_rep_select) 272 dontTouch(s0_hw_prf_select) 273 dontTouch(s0_int_iss_select) 274 dontTouch(s0_vec_iss_select) 275 dontTouch(s0_l2l_fwd_select) 276 277 s0_valid := (s0_super_ld_rep_valid || 278 s0_ld_fast_rep_valid || 279 s0_ld_rep_valid || 280 s0_high_conf_prf_valid || 281 s0_int_iss_valid || 282 s0_vec_iss_valid || 283 s0_l2l_fwd_valid || 284 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 285 286 // which is S0's out is ready and dcache is ready 287 val s0_try_ptr_chasing = s0_l2l_fwd_select 288 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 289 val s0_ptr_chasing_vaddr = io.l2l_fwd_in.data(5, 0) +& io.ld_fast_imm(5, 0) 290 val s0_ptr_chasing_canceled = WireInit(false.B) 291 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 292 293 // prefetch related ctrl signal 294 val s0_prf = Wire(Bool()) 295 val s0_prf_rd = Wire(Bool()) 296 val s0_prf_wr = Wire(Bool()) 297 val s0_hw_prf = s0_hw_prf_select 298 299 // query DTLB 300 io.tlb.req.valid := s0_valid 301 io.tlb.req.bits.cmd := Mux(s0_prf, 302 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 303 TlbCmd.read 304 ) 305 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.prefetch_req.bits.paddr, s0_vaddr) 306 io.tlb.req.bits.size := LSUOpType.size(s0_uop.ctrl.fuOpType) 307 io.tlb.req.bits.kill := s0_kill 308 io.tlb.req.bits.memidx.is_ld := true.B 309 io.tlb.req.bits.memidx.is_st := false.B 310 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 311 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 312 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 313 io.tlb.req.bits.debug.pc := s0_uop.cf.pc 314 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 315 316 // query DCache 317 io.dcache.req.valid := s0_valid 318 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 319 MemoryOpConstants.M_PFR, 320 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD) 321 ) 322 io.dcache.req.bits.vaddr := s0_vaddr 323 io.dcache.req.bits.mask := s0_mask 324 io.dcache.req.bits.data := DontCare 325 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 326 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 327 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 328 io.dcache.req.bits.replayCarry := s0_rep_carry 329 io.dcache.req.bits.id := DontCare // TODO: update cache meta 330 331 // load flow priority mux 332 def fromNullSource() = { 333 s0_vaddr := 0.U 334 s0_mask := 0.U 335 s0_uop := 0.U.asTypeOf(new MicroOp) 336 s0_try_l2l := false.B 337 s0_has_rob_entry := false.B 338 s0_rsIdx := 0.U 339 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 340 s0_mshrid := 0.U 341 s0_isFirstIssue := false.B 342 s0_fast_rep := false.B 343 s0_ld_rep := false.B 344 s0_l2l_fwd := false.B 345 s0_prf := false.B 346 s0_prf_rd := false.B 347 s0_prf_wr := false.B 348 s0_sched_idx := 0.U 349 } 350 351 def fromFastReplaySource(src: LqWriteBundle) = { 352 s0_vaddr := src.vaddr 353 s0_mask := src.mask 354 s0_uop := src.uop 355 s0_try_l2l := false.B 356 s0_has_rob_entry := src.hasROBEntry 357 s0_rep_carry := src.rep_info.rep_carry 358 s0_mshrid := src.rep_info.mshr_id 359 s0_rsIdx := src.rsIdx 360 s0_isFirstIssue := false.B 361 s0_fast_rep := true.B 362 s0_ld_rep := src.isLoadReplay 363 s0_l2l_fwd := false.B 364 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 365 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 366 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 367 s0_sched_idx := src.schedIndex 368 } 369 370 def fromNormalReplaySource(src: LsPipelineBundle) = { 371 s0_vaddr := src.vaddr 372 s0_mask := genVWmask(src.vaddr, src.uop.ctrl.fuOpType(1, 0)) 373 s0_uop := src.uop 374 s0_try_l2l := false.B 375 s0_has_rob_entry := true.B 376 s0_rsIdx := src.rsIdx 377 s0_rep_carry := src.replayCarry 378 s0_mshrid := src.mshrid 379 s0_isFirstIssue := false.B 380 s0_fast_rep := false.B 381 s0_ld_rep := true.B 382 s0_l2l_fwd := false.B 383 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 384 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 385 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 386 s0_sched_idx := src.schedIndex 387 } 388 389 def fromPrefetchSource(src: L1PrefetchReq) = { 390 s0_vaddr := src.getVaddr() 391 s0_mask := 0.U 392 s0_uop := DontCare 393 s0_try_l2l := false.B 394 s0_has_rob_entry := false.B 395 s0_rsIdx := 0.U 396 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 397 s0_mshrid := 0.U 398 s0_isFirstIssue := false.B 399 s0_fast_rep := false.B 400 s0_ld_rep := false.B 401 s0_l2l_fwd := false.B 402 s0_prf := true.B 403 s0_prf_rd := !src.is_store 404 s0_prf_wr := src.is_store 405 s0_sched_idx := 0.U 406 } 407 408 def fromIntIssueSource(src: ExuInput) = { 409 s0_vaddr := src.src(0) + SignExt(src.uop.ctrl.imm(11, 0), VAddrBits) 410 s0_mask := genVWmask(s0_vaddr, src.uop.ctrl.fuOpType(1,0)) 411 s0_uop := src.uop 412 s0_try_l2l := false.B 413 s0_has_rob_entry := true.B 414 s0_rsIdx := io.rsIdx 415 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 416 s0_mshrid := 0.U 417 s0_isFirstIssue := true.B 418 s0_fast_rep := false.B 419 s0_ld_rep := false.B 420 s0_l2l_fwd := false.B 421 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 422 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 423 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 424 s0_sched_idx := 0.U 425 } 426 427 def fromVecIssueSource() = { 428 s0_vaddr := 0.U 429 s0_mask := 0.U 430 s0_uop := 0.U.asTypeOf(new MicroOp) 431 s0_try_l2l := false.B 432 s0_has_rob_entry := false.B 433 s0_rsIdx := 0.U 434 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 435 s0_mshrid := 0.U 436 s0_isFirstIssue := false.B 437 s0_fast_rep := false.B 438 s0_ld_rep := false.B 439 s0_l2l_fwd := false.B 440 s0_prf := false.B 441 s0_prf_rd := false.B 442 s0_prf_wr := false.B 443 s0_sched_idx := 0.U 444 } 445 446 def fromLoadToLoadSource(src: LoadToLoadIO) = { 447 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 448 s0_mask := genVWmask(s0_vaddr, io.ld_fast_fuOpType(1, 0)) 449 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 450 // Assume the pointer chasing is always ld. 451 s0_uop.ctrl.fuOpType := io.ld_fast_fuOpType 452 s0_try_l2l := true.B 453 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 454 // because these signals will be updated in S1 455 s0_has_rob_entry := false.B 456 s0_rsIdx := 0.U 457 s0_mshrid := 0.U 458 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 459 s0_isFirstIssue := true.B 460 s0_fast_rep := false.B 461 s0_ld_rep := false.B 462 s0_l2l_fwd := true.B 463 s0_prf := false.B 464 s0_prf_rd := false.B 465 s0_prf_wr := false.B 466 s0_sched_idx := 0.U 467 } 468 469 // set default 470 s0_uop := DontCare 471 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 472 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.fast_rep_in.bits) } 473 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 474 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.prefetch_req.bits) } 475 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.ldin.bits) } 476 .elsewhen (s0_vec_iss_select) { fromVecIssueSource() } 477 .otherwise { 478 if (EnableLoadToLoadForward) { 479 fromLoadToLoadSource(io.l2l_fwd_in) 480 } else { 481 fromNullSource() 482 } 483 } 484 485 // address align check 486 val s0_addr_aligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 487 "b00".U -> true.B, //b 488 "b01".U -> (s0_vaddr(0) === 0.U), //h 489 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 490 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 491 )) 492 493 // accept load flow if dcache ready (tlb is always ready) 494 // TODO: prefetch need writeback to loadQueueFlag 495 s0_out := DontCare 496 s0_out.rsIdx := s0_rsIdx 497 s0_out.vaddr := s0_vaddr 498 s0_out.mask := s0_mask 499 s0_out.uop := s0_uop 500 s0_out.isFirstIssue := s0_isFirstIssue 501 s0_out.hasROBEntry := s0_has_rob_entry 502 s0_out.isPrefetch := s0_prf 503 s0_out.isHWPrefetch := s0_hw_prf 504 s0_out.isFastReplay := s0_fast_rep 505 s0_out.isLoadReplay := s0_ld_rep 506 s0_out.isFastPath := s0_l2l_fwd 507 s0_out.mshrid := s0_mshrid 508 s0_out.uop.cf.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned 509 s0_out.forward_tlDchannel := s0_super_ld_rep_select 510 when(io.tlb.req.valid && s0_isFirstIssue) { 511 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 512 }.otherwise{ 513 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 514 } 515 s0_out.schedIndex := s0_sched_idx 516 517 // load fast replay 518 io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 519 520 // load flow source ready 521 // cache missed load has highest priority 522 // always accept cache missed load flow from load replay queue 523 io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 524 525 // accept load flow from rs when: 526 // 1) there is no lsq-replayed load 527 // 2) there is no fast replayed load 528 // 3) there is no high confidence prefetch request 529 io.ldin.ready := (s0_can_go && io.dcache.req.ready && s0_int_iss_ready) 530 531 // for hw prefetch load flow feedback, to be added later 532 // io.prefetch_in.ready := s0_hw_prf_select 533 534 // dcache replacement extra info 535 // TODO: should prefetch load update replacement? 536 io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.replay.bits.replacementUpdated, false.B) 537 538 XSDebug(io.dcache.req.fire, 539 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 540 ) 541 XSDebug(s0_valid, 542 p"S0: pc ${Hexadecimal(s0_out.uop.cf.pc)}, lId ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 543 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 544 545 // Pipeline 546 // -------------------------------------------------------------------------------- 547 // stage 1 548 // -------------------------------------------------------------------------------- 549 // TLB resp (send paddr to dcache) 550 val s1_valid = RegInit(false.B) 551 val s1_in = Wire(new LqWriteBundle) 552 val s1_out = Wire(new LqWriteBundle) 553 val s1_kill = Wire(Bool()) 554 val s1_can_go = s2_ready 555 val s1_fire = s1_valid && !s1_kill && s1_can_go 556 557 s1_ready := !s1_valid || s1_kill || s2_ready 558 when (s0_fire) { s1_valid := true.B } 559 .elsewhen (s1_fire) { s1_valid := false.B } 560 .elsewhen (s1_kill) { s1_valid := false.B } 561 s1_in := RegEnable(s0_out, s0_fire) 562 563 val s1_fast_rep_dly_err = RegNext(io.fast_rep_in.bits.delayedLoadError) 564 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 565 val s1_l2l_fwd_dly_err = RegNext(io.l2l_fwd_in.dly_ld_err) 566 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 567 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 568 val s1_vaddr_hi = Wire(UInt()) 569 val s1_vaddr_lo = Wire(UInt()) 570 val s1_vaddr = Wire(UInt()) 571 val s1_paddr_dup_lsu = Wire(UInt()) 572 val s1_paddr_dup_dcache = Wire(UInt()) 573 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.cf.exceptionVec, lduCfg).asUInt.orR // af & pf exception were modified below. 574 val s1_tlb_miss = io.tlb.resp.bits.miss 575 val s1_prf = s1_in.isPrefetch 576 val s1_hw_prf = s1_in.isHWPrefetch 577 val s1_sw_prf = s1_prf && !s1_hw_prf 578 val s1_tlb_memidx = io.tlb.resp.bits.memidx 579 580 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 581 s1_vaddr_lo := s1_in.vaddr(5, 0) 582 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 583 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 584 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 585 586 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_in.uop.lqIdx.value) { 587 // printf("load idx = %d\n", s1_tlb_memidx.idx) 588 s1_out.uop.debugInfo.tlbRespTime := GTimer() 589 } 590 591 io.tlb.req_kill := s1_kill 592 io.tlb.resp.ready := true.B 593 594 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 595 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 596 io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 597 598 // store to load forwarding 599 io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 600 io.sbuffer.vaddr := s1_vaddr 601 io.sbuffer.paddr := s1_paddr_dup_lsu 602 io.sbuffer.uop := s1_in.uop 603 io.sbuffer.sqIdx := s1_in.uop.sqIdx 604 io.sbuffer.mask := s1_in.mask 605 io.sbuffer.pc := s1_in.uop.cf.pc // FIXME: remove it 606 607 io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 608 io.lsq.forward.vaddr := s1_vaddr 609 io.lsq.forward.paddr := s1_paddr_dup_lsu 610 io.lsq.forward.uop := s1_in.uop 611 io.lsq.forward.sqIdx := s1_in.uop.sqIdx 612 io.lsq.forward.sqIdxMask := 0.U 613 io.lsq.forward.mask := s1_in.mask 614 io.lsq.forward.pc := s1_in.uop.cf.pc // FIXME: remove it 615 616 // st-ld violation query 617 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 618 io.stld_nuke_query(w).valid && // query valid 619 isAfter(s1_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 620 // TODO: Fix me when vector instruction 621 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 622 (s1_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 623 })).asUInt.orR && !s1_tlb_miss 624 625 s1_out := s1_in 626 s1_out.vaddr := s1_vaddr 627 s1_out.paddr := s1_paddr_dup_lsu 628 s1_out.tlbMiss := s1_tlb_miss 629 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 630 s1_out.rsIdx := s1_in.rsIdx 631 s1_out.rep_info.debug := s1_in.uop.debugInfo 632 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 633 s1_out.lateKill := s1_late_kill 634 635 when (!s1_late_kill) { 636 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 637 // af & pf exception were modified 638 s1_out.uop.cf.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 639 s1_out.uop.cf.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 640 } .otherwise { 641 s1_out.uop.cf.exceptionVec(loadAddrMisaligned) := false.B 642 s1_out.uop.cf.exceptionVec(loadAccessFault) := s1_late_kill 643 } 644 645 // pointer chasing 646 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 647 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 648 val s1_fu_op_type_not_ld = WireInit(false.B) 649 val s1_not_fast_match = WireInit(false.B) 650 val s1_addr_mismatch = WireInit(false.B) 651 val s1_addr_misaligned = WireInit(false.B) 652 val s1_ptr_chasing_canceled = WireInit(false.B) 653 val s1_cancel_ptr_chasing = WireInit(false.B) 654 655 s1_kill := s1_late_kill || 656 s1_cancel_ptr_chasing || 657 s1_in.uop.robIdx.needFlush(io.redirect) || 658 RegEnable(s0_kill, false.B, io.ldin.valid || io.replay.valid || io.l2l_fwd_in.valid || io.fast_rep_in.valid) 659 660 if (EnableLoadToLoadForward) { 661 // Sometimes, we need to cancel the load-load forwarding. 662 // These can be put at S0 if timing is bad at S1. 663 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 664 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 665 // Case 1: the address is misaligned, kill s1 666 s1_addr_misaligned := LookupTree(s1_in.uop.ctrl.fuOpType(1, 0), List( 667 "b00".U -> false.B, //b 668 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 669 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 670 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 671 )) 672 // Case 2: this load-load uop is cancelled 673 s1_ptr_chasing_canceled := !io.ldin.valid 674 675 when (s1_try_ptr_chasing) { 676 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 677 678 s1_in.uop := io.ldin.bits.uop 679 s1_in.rsIdx := io.rsIdx 680 s1_in.isFirstIssue := io.isFirstIssue 681 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 682 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 683 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 684 685 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 686 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 687 s1_in.uop.debugInfo.tlbRespTime := GTimer() 688 } 689 when (!s1_cancel_ptr_chasing) { 690 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.replay.fire && !io.fast_rep_in.fire 691 when (s1_try_ptr_chasing) { 692 io.ldin.ready := true.B 693 } 694 } 695 } 696 697 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 698 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 699 // to enable load-load, sqIdxMask must be calculated based on ldin.uop 700 // If the timing here is not OK, load-load forwarding has to be disabled. 701 // Or we calculate sqIdxMask at RS?? 702 io.lsq.forward.sqIdxMask := s1_sqIdx_mask 703 if (EnableLoadToLoadForward) { 704 when (s1_try_ptr_chasing) { 705 io.lsq.forward.sqIdxMask := UIntToMask(io.ldin.bits.uop.sqIdx.value, StoreQueueSize) 706 } 707 } 708 709 io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel 710 io.forward_mshr.mshrid := s1_out.mshrid 711 io.forward_mshr.paddr := s1_out.paddr 712 713 XSDebug(s1_valid, 714 p"S1: pc ${Hexadecimal(s1_out.uop.cf.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 715 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 716 717 // Pipeline 718 // -------------------------------------------------------------------------------- 719 // stage 2 720 // -------------------------------------------------------------------------------- 721 // s2: DCache resp 722 val s2_valid = RegInit(false.B) 723 val s2_in = Wire(new LqWriteBundle) 724 val s2_out = Wire(new LqWriteBundle) 725 val s2_kill = Wire(Bool()) 726 val s2_can_go = s3_ready 727 val s2_fire = s2_valid && !s2_kill && s2_can_go 728 729 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 730 s2_ready := !s2_valid || s2_kill || s3_ready 731 when (s1_fire) { s2_valid := true.B } 732 .elsewhen (s2_fire) { s2_valid := false.B } 733 .elsewhen (s2_kill) { s2_valid := false.B } 734 s2_in := RegEnable(s1_out, s1_fire) 735 736 val s2_pmp = WireInit(io.pmp) 737 val s2_static_pm = RegNext(io.tlb.resp.bits.static_pm) 738 when (s2_static_pm.valid) { 739 s2_pmp.ld := false.B 740 s2_pmp.st := false.B 741 s2_pmp.instr := false.B 742 s2_pmp.mmio := s2_static_pm.bits 743 } 744 val s2_prf = s2_in.isPrefetch 745 val s2_hw_prf = s2_in.isHWPrefetch 746 747 // exception that may cause load addr to be invalid / illegal 748 // if such exception happen, that inst and its exception info 749 // will be force writebacked to rob 750 val s2_exception_vec = WireInit(s2_in.uop.cf.exceptionVec) 751 when (!s2_in.lateKill) { 752 s2_exception_vec(loadAccessFault) := s2_in.uop.cf.exceptionVec(loadAccessFault) || s2_pmp.ld 753 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 754 when (s2_prf || s2_in.tlbMiss) { 755 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 756 } 757 } 758 val s2_exception = ExceptionNO.selectByFu(s2_exception_vec, lduCfg).asUInt.orR 759 760 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 761 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.forward_mshr.forward() 762 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 763 764 // writeback access fault caused by ecc error / bus error 765 // * ecc data error is slow to generate, so we will not use it until load stage 3 766 // * in load stage 3, an extra signal io.load_error will be used to 767 val s2_actually_mmio = s2_pmp.mmio 768 val s2_mmio = !s2_prf && 769 s2_actually_mmio && 770 !s2_exception && 771 !s2_in.tlbMiss 772 773 val s2_full_fwd = Wire(Bool()) 774 val s2_mem_amb = s2_in.uop.cf.storeSetHit && 775 io.lsq.forward.addrInvalid 776 777 val s2_tlb_miss = s2_in.tlbMiss 778 val s2_fwd_fail = io.lsq.forward.dataInvalid 779 val s2_dcache_miss = io.dcache.resp.bits.miss && 780 !s2_fwd_frm_d_chan_or_mshr && 781 !s2_full_fwd 782 783 val s2_mq_nack = io.dcache.s2_mq_nack && 784 !s2_fwd_frm_d_chan_or_mshr && 785 !s2_full_fwd 786 787 val s2_bank_conflict = io.dcache.s2_bank_conflict && 788 !s2_fwd_frm_d_chan_or_mshr && 789 !s2_full_fwd 790 791 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail && 792 !s2_fwd_frm_d_chan_or_mshr && 793 !s2_full_fwd 794 795 val s2_rar_nack = io.lsq.ldld_nuke_query.req.valid && 796 !io.lsq.ldld_nuke_query.req.ready 797 798 val s2_raw_nack = io.lsq.stld_nuke_query.req.valid && 799 !io.lsq.stld_nuke_query.req.ready 800 // st-ld violation query 801 // NeedFastRecovery Valid when 802 // 1. Fast recovery query request Valid. 803 // 2. Load instruction is younger than requestors(store instructions). 804 // 3. Physical address match. 805 // 4. Data contains. 806 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 807 io.stld_nuke_query(w).valid && // query valid 808 isAfter(s2_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 809 // TODO: Fix me when vector instruction 810 (s2_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 811 (s2_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 812 })).asUInt.orR && !s2_tlb_miss || s2_in.rep_info.nuke 813 814 val s2_cache_handled = io.dcache.resp.bits.handled 815 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 816 io.dcache.resp.bits.tag_error 817 818 val s2_troublem = !s2_exception && 819 !s2_mmio && 820 !s2_prf && 821 !s2_in.lateKill 822 823 io.dcache.resp.ready := true.B 824 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf || s2_in.lateKill) 825 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 826 827 // fast replay require 828 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 829 val s2_nuke_fast_rep = !s2_mq_nack && 830 !s2_dcache_miss && 831 !s2_bank_conflict && 832 !s2_wpu_pred_fail && 833 !s2_rar_nack && 834 !s2_raw_nack && 835 s2_nuke 836 837 val s2_hint_fast_rep = !s2_mq_nack && 838 s2_dcache_miss && 839 s2_cache_handled && 840 io.l2_hint.valid && 841 io.l2_hint.bits.sourceId === io.dcache.resp.bits.mshr_id 842 843 844 val s2_fast_rep = !s2_mem_amb && 845 !s2_tlb_miss && 846 !s2_fwd_fail && 847 (s2_dcache_fast_rep || s2_hint_fast_rep || s2_nuke_fast_rep) && 848 s2_troublem 849 850 // need allocate new entry 851 val s2_can_query = !s2_mem_amb && 852 !s2_tlb_miss && 853 !s2_fwd_fail && 854 !s2_dcache_fast_rep && 855 s2_troublem 856 857 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 858 859 // ld-ld violation require 860 io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 861 io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 862 io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 863 io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 864 io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 865 866 // st-ld violation require 867 io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 868 io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 869 io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 870 io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 871 io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 872 873 // merge forward result 874 // lsq has higher priority than sbuffer 875 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 876 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 877 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.lsq.forward.dataInvalid 878 // generate XLEN/8 Muxs 879 for (i <- 0 until VLEN / 8) { 880 s2_fwd_mask(i) := io.lsq.forward.forwardMask(i) || io.sbuffer.forwardMask(i) 881 s2_fwd_data(i) := Mux(io.lsq.forward.forwardMask(i), io.lsq.forward.forwardData(i), io.sbuffer.forwardData(i)) 882 } 883 884 XSDebug(s2_fire, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 885 s2_in.uop.cf.pc, 886 io.lsq.forward.forwardData.asUInt, io.lsq.forward.forwardMask.asUInt, 887 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 888 ) 889 890 // 891 s2_out := s2_in 892 s2_out.data := 0.U // data will be generated in load s3 893 s2_out.uop.ctrl.fpWen := s2_in.uop.ctrl.fpWen && !s2_exception 894 s2_out.mmio := s2_mmio 895 s2_out.uop.ctrl.flushPipe := false.B 896 s2_out.uop.cf.exceptionVec := s2_exception_vec 897 s2_out.forwardMask := s2_fwd_mask 898 s2_out.forwardData := s2_fwd_data 899 s2_out.handledByMSHR := s2_cache_handled 900 s2_out.miss := s2_dcache_miss && s2_troublem 901 s2_out.feedbacked := io.feedback_fast.valid 902 903 // Generate replay signal caused by: 904 // * st-ld violation check 905 // * tlb miss 906 // * dcache replay 907 // * forward data invalid 908 // * dcache miss 909 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 910 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 911 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 912 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 913 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 914 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 915 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 916 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 917 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 918 s2_out.rep_info.nuke := s2_nuke && s2_troublem 919 s2_out.rep_info.full_fwd := s2_data_fwded 920 s2_out.rep_info.data_inv_sq_idx := io.lsq.forward.dataInvalidSqIdx 921 s2_out.rep_info.addr_inv_sq_idx := io.lsq.forward.addrInvalidSqIdx 922 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 923 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 924 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 925 s2_out.rep_info.debug := s2_in.uop.debugInfo 926 927 // if forward fail, replay this inst from fetch 928 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 929 // if ld-ld violation is detected, replay from this inst from fetch 930 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 931 // io.out.bits.uop.ctrl.replayInst := false.B 932 933 // to be removed 934 io.feedback_fast.valid := s2_valid && // inst is valid 935 !s2_in.isLoadReplay && // already feedbacked 936 io.lq_rep_full && // LoadQueueReplay is full 937 s2_out.rep_info.need_rep && // need replay 938 !s2_exception && // no exception is triggered 939 !s2_hw_prf // not hardware prefetch 940 io.feedback_fast.bits.hit := false.B 941 io.feedback_fast.bits.flushState := s2_in.ptwBack 942 io.feedback_fast.bits.rsIdx := s2_in.rsIdx 943 io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull 944 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 945 946 // fast wakeup 947 io.fast_uop.valid := RegNext( 948 !io.dcache.s1_disable_fast_wakeup && 949 s1_valid && 950 !s1_kill && 951 !io.tlb.resp.bits.fast_miss && 952 !io.lsq.forward.dataInvalidFast 953 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_mmio) 954 io.fast_uop.bits := RegNext(s1_out.uop) 955 956 // 957 io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, s1_fire) 958 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 959 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 960 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 961 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 962 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 963 if (env.FPGAPlatform){ 964 io.dcache.s0_pc := DontCare 965 io.dcache.s1_pc := DontCare 966 io.dcache.s2_pc := DontCare 967 }else{ 968 io.dcache.s0_pc := s0_out.uop.cf.pc 969 io.dcache.s1_pc := s1_out.uop.cf.pc 970 io.dcache.s2_pc := s2_out.uop.cf.pc 971 } 972 io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 973 974 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready 975 val s2_ld_valid_dup = RegInit(0.U(6.W)) 976 s2_ld_valid_dup := 0x0.U(6.W) 977 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 978 when (s1_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 979 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 980 981 // Pipeline 982 // -------------------------------------------------------------------------------- 983 // stage 3 984 // -------------------------------------------------------------------------------- 985 // writeback and update load queue 986 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 987 val s3_in = RegEnable(s2_out, s2_fire) 988 val s3_out = Wire(Valid(new ExuOutput)) 989 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, s2_fire) 990 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 991 val s3_fast_rep = Wire(Bool()) 992 val s3_troublem = RegNext(s2_troublem) 993 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 994 s3_ready := !s3_valid || s3_kill || io.ldout.ready 995 996 // forwrad last beat 997 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 998 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, s2_valid) 999 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid) 1000 val s3_nuke = VecInit((0 until StorePipelineWidth).map(w => { 1001 io.stld_nuke_query(w).valid && // query valid 1002 isAfter(s3_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 1003 // TODO: Fix me when vector instruction 1004 (s3_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 1005 (s3_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 1006 })).asUInt.orR && !s3_in.tlbMiss || s3_in.rep_info.nuke 1007 1008 1009 // s3 load fast replay 1010 io.fast_rep_out.valid := s3_valid && s3_fast_rep && !s3_in.uop.robIdx.needFlush(io.redirect) 1011 io.fast_rep_out.bits := s3_in 1012 1013 io.lsq.ldin.valid := s3_valid && (!s3_fast_rep || !io.fast_rep_out.ready) && !s3_in.feedbacked && !s3_in.lateKill 1014 io.lsq.ldin.bits := s3_in 1015 io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1016 1017 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1018 io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1019 io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 1020 1021 val s3_dly_ld_err = 1022 if (EnableAccurateLoadError) { 1023 (s3_in.lateKill || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1024 } else { 1025 WireInit(false.B) 1026 } 1027 io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1028 io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1029 io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1030 1031 val s3_vp_match_fail = RegNext(io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid) && s3_troublem 1032 val s3_ldld_rep_inst = 1033 io.lsq.ldld_nuke_query.resp.valid && 1034 io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1035 RegNext(io.csrCtrl.ldld_vio_check_enable) 1036 1037 val s3_rep_info = WireInit(s3_in.rep_info) 1038 s3_rep_info.wpu_fail := s3_in.rep_info.wpu_fail && !s3_fwd_frm_d_chan_valid && s3_troublem 1039 s3_rep_info.bank_conflict := s3_in.rep_info.bank_conflict && !s3_fwd_frm_d_chan_valid && s3_troublem 1040 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1041 s3_rep_info.nuke := s3_nuke && s3_troublem 1042 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 1043 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1044 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1045 !s3_in.uop.cf.exceptionVec(loadAddrMisaligned) && 1046 s3_troublem 1047 1048 val s3_exception = ExceptionNO.selectByFu(s3_in.uop.cf.exceptionVec, lduCfg).asUInt.orR 1049 when ((s3_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1050 io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1051 } .otherwise { 1052 io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1053 } 1054 1055 // Int load, if hit, will be writebacked at s3 1056 s3_out.valid := s3_valid && !io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio 1057 s3_out.bits.uop := s3_in.uop 1058 s3_out.bits.uop.cf.exceptionVec(loadAccessFault) := s3_dly_ld_err || s3_in.uop.cf.exceptionVec(loadAccessFault) 1059 s3_out.bits.uop.ctrl.replayInst := s3_rep_frm_fetch 1060 s3_out.bits.data := s3_in.data 1061 s3_out.bits.redirectValid := false.B 1062 s3_out.bits.redirect := DontCare 1063 s3_out.bits.debug.isMMIO := s3_in.mmio 1064 s3_out.bits.debug.isPerfCnt := false.B 1065 s3_out.bits.debug.paddr := s3_in.paddr 1066 s3_out.bits.debug.vaddr := s3_in.vaddr 1067 s3_out.bits.fflags := DontCare 1068 1069 when (s3_force_rep) { 1070 s3_out.bits.uop.cf.exceptionVec := 0.U.asTypeOf(s3_in.uop.cf.exceptionVec.cloneType) 1071 } 1072 1073 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1074 1075 io.lsq.ldin.bits.uop := s3_out.bits.uop 1076 1077 val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep 1078 io.lsq.ldld_nuke_query.revoke := s3_revoke 1079 io.lsq.stld_nuke_query.revoke := s3_revoke 1080 1081 // feedback slow 1082 s3_fast_rep := RegNext(s2_fast_rep) && 1083 !s3_in.feedbacked && 1084 !s3_in.lateKill && 1085 !s3_rep_frm_fetch && 1086 !s3_exception 1087 1088 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.fast_rep_out.ready) && !s3_in.feedbacked 1089 1090 // 1091 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting 1092 io.feedback_slow.bits.hit := !io.lsq.ldin.bits.rep_info.need_rep || io.lsq.ldin.ready 1093 io.feedback_slow.bits.flushState := s3_in.ptwBack 1094 io.feedback_slow.bits.rsIdx := s3_in.rsIdx 1095 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1096 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1097 1098 val s3_ld_wb_meta = Mux(s3_out.valid, s3_out.bits, io.lsq.uncache.bits) 1099 1100 // data from load queue refill 1101 val s3_ld_raw_data_frm_uncache = io.lsq.ld_raw_data 1102 val s3_merged_data_frm_uncache = s3_ld_raw_data_frm_uncache.mergedData() 1103 val s3_picked_data_frm_uncache = LookupTree(s3_ld_raw_data_frm_uncache.addrOffset, List( 1104 "b000".U -> s3_merged_data_frm_uncache(63, 0), 1105 "b001".U -> s3_merged_data_frm_uncache(63, 8), 1106 "b010".U -> s3_merged_data_frm_uncache(63, 16), 1107 "b011".U -> s3_merged_data_frm_uncache(63, 24), 1108 "b100".U -> s3_merged_data_frm_uncache(63, 32), 1109 "b101".U -> s3_merged_data_frm_uncache(63, 40), 1110 "b110".U -> s3_merged_data_frm_uncache(63, 48), 1111 "b111".U -> s3_merged_data_frm_uncache(63, 56) 1112 )) 1113 val s3_ld_data_frm_uncache = rdataHelper(s3_ld_raw_data_frm_uncache.uop, s3_picked_data_frm_uncache) 1114 1115 // data from dcache hit 1116 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1117 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1118 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1119 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1120 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1121 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1122 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, s2_valid) || s3_fwd_frm_d_chan_valid 1123 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1124 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, s2_valid) 1125 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1126 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, s2_valid) 1127 1128 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1129 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1130 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1131 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1132 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1133 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1134 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1135 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1136 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1137 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1138 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1139 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1140 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1141 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1142 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1143 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1144 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1145 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1146 )) 1147 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1148 1149 // FIXME: add 1 cycle delay ? 1150 io.lsq.uncache.ready := !s3_out.valid 1151 io.ldout.bits := s3_ld_wb_meta 1152 io.ldout.bits.data := Mux(s3_out.valid, s3_ld_data_frm_cache, s3_ld_data_frm_uncache) 1153 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1154 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid 1155 1156 1157 // fast load to load forward 1158 io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill 1159 io.l2l_fwd_out.data := s3_ld_data_frm_cache 1160 io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1161 1162 // trigger 1163 val last_valid_data = RegNext(RegEnable(io.ldout.bits.data, io.ldout.fire)) 1164 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1165 val lq_ld_addr_trig_hit_vec = io.lsq.trigger.lqLoadAddrTriggerHitVec 1166 (0 until 3).map{i => { 1167 val tdata2 = RegNext(io.trigger(i).tdata2) 1168 val matchType = RegNext(io.trigger(i).matchType) 1169 val tEnable = RegNext(io.trigger(i).tEnable) 1170 1171 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s2_out.vaddr), tdata2, matchType, tEnable) 1172 io.trigger(i).addrHit := Mux(s3_out.valid, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1173 io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1174 }} 1175 io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1176 1177 // FIXME: please move this part to LoadQueueReplay 1178 io.debug_ls := DontCare 1179 1180 // Topdown 1181 io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1182 io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1183 io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1184 io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1185 io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1186 io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1187 1188 // perf cnt 1189 XSPerfAccumulate("s0_in_valid", io.ldin.valid) 1190 XSPerfAccumulate("s0_in_block", io.ldin.valid && !io.ldin.fire) 1191 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1192 XSPerfAccumulate("s0_lsq_fire_first_issue", io.replay.fire) 1193 XSPerfAccumulate("s0_ldu_fire_first_issue", io.ldin.fire && s0_isFirstIssue) 1194 XSPerfAccumulate("s0_fast_replay_issue", io.fast_rep_in.fire) 1195 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1196 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1197 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12)) 1198 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12)) 1199 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1200 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1201 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1202 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1203 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1204 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.prefetch_req.valid && !s0_hw_prf_select) 1205 XSPerfAccumulate("s0_hardware_prefetch_total", io.prefetch_req.valid) 1206 1207 XSPerfAccumulate("s1_in_valid", s1_valid) 1208 XSPerfAccumulate("s1_in_fire", s1_fire) 1209 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1210 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1211 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1212 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1213 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1214 1215 XSPerfAccumulate("s2_in_valid", s2_valid) 1216 XSPerfAccumulate("s2_in_fire", s2_fire) 1217 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1218 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.dcache.resp.bits.miss) 1219 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1220 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1221 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1222 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1223 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1224 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1225 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1226 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1227 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1228 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.dcache.resp.bits.miss) // prefetch req miss in l1 1229 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.dcache.resp.bits.miss) // prefetch req hit in l1 1230 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.dcache.resp.bits.miss && !s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1231 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1232 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1233 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1234 1235 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1236 1237 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1238 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1239 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1240 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1241 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1242 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1243 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1244 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1245 1246 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1247 // hardware performance counter 1248 val perfEvents = Seq( 1249 ("load_s0_in_fire ", s0_fire ), 1250 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1251 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1252 ("load_s1_in_fire ", s0_fire ), 1253 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1254 ("load_s2_in_fire ", s1_fire ), 1255 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1256 ) 1257 generatePerfEvent() 1258 1259 when(io.ldout.fire){ 1260 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 1261 } 1262 // end 1263}