1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10import xiangshan.backend.fu.fpu.boxF32ToF64 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val forward = new LoadForwardQueryIO 16} 17 18// Load Pipeline Stage 0 19// Generate addr, use addr to query DCache and DTLB 20class LoadUnit_S0 extends XSModule { 21 val io = IO(new Bundle() { 22 val in = Flipped(Decoupled(new ExuInput)) 23 val out = Decoupled(new LsPipelineBundle) 24 val dtlbReq = DecoupledIO(new TlbReq) 25 val dcacheReq = DecoupledIO(new DCacheLoadReq) 26 }) 27 28 val s0_uop = io.in.bits.uop 29 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 30 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 31 32 // query DTLB 33 io.dtlbReq.valid := io.in.valid 34 io.dtlbReq.bits.vaddr := s0_vaddr 35 io.dtlbReq.bits.cmd := TlbCmd.read 36 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 37 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 38 39 // query DCache 40 io.dcacheReq.valid := io.in.valid 41 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 42 io.dcacheReq.bits.addr := s0_vaddr 43 io.dcacheReq.bits.mask := s0_mask 44 io.dcacheReq.bits.data := DontCare 45 46 // TODO: update cache meta 47 io.dcacheReq.bits.meta.id := DontCare 48 io.dcacheReq.bits.meta.vaddr := s0_vaddr 49 io.dcacheReq.bits.meta.paddr := DontCare 50 io.dcacheReq.bits.meta.uop := s0_uop 51 io.dcacheReq.bits.meta.mmio := false.B 52 io.dcacheReq.bits.meta.tlb_miss := false.B 53 io.dcacheReq.bits.meta.mask := s0_mask 54 io.dcacheReq.bits.meta.replay := false.B 55 56 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 57 "b00".U -> true.B, //b 58 "b01".U -> (s0_vaddr(0) === 0.U), //h 59 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 60 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 61 )) 62 63 io.out.valid := io.in.valid && io.dcacheReq.ready 64 65 io.out.bits := DontCare 66 io.out.bits.vaddr := s0_vaddr 67 io.out.bits.mask := s0_mask 68 io.out.bits.uop := s0_uop 69 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 70 71 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 72 73 XSDebug(io.dcacheReq.fire(), 74 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 75 ) 76} 77 78 79// Load Pipeline Stage 1 80// TLB resp (send paddr to dcache) 81class LoadUnit_S1 extends XSModule { 82 val io = IO(new Bundle() { 83 val in = Flipped(Decoupled(new LsPipelineBundle)) 84 val out = Decoupled(new LsPipelineBundle) 85 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 86 val tlbFeedback = ValidIO(new TlbFeedback) 87 val dcachePAddr = Output(UInt(PAddrBits.W)) 88 val sbuffer = new LoadForwardQueryIO 89 val lsq = new LoadForwardQueryIO 90 }) 91 92 val s1_uop = io.in.bits.uop 93 val s1_paddr = io.dtlbResp.bits.paddr 94 val s1_tlb_miss = io.dtlbResp.bits.miss 95 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) && !io.out.bits.uop.cf.exceptionVec.asUInt.orR 96 val s1_mask = io.in.bits.mask 97 98 io.out.bits := io.in.bits // forwardXX field will be updated in s1 99 100 io.dtlbResp.ready := true.B 101 // feedback tlb result to RS 102 io.tlbFeedback.valid := io.in.valid 103 io.tlbFeedback.bits.hit := !s1_tlb_miss 104 io.tlbFeedback.bits.roqIdx := s1_uop.roqIdx 105 106 io.dcachePAddr := s1_paddr 107 108 // load forward query datapath 109 io.sbuffer.valid := io.in.valid 110 io.sbuffer.paddr := s1_paddr 111 io.sbuffer.uop := s1_uop 112 io.sbuffer.sqIdx := s1_uop.sqIdx 113 io.sbuffer.mask := s1_mask 114 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 115 116 io.lsq.valid := io.in.valid 117 io.lsq.paddr := s1_paddr 118 io.lsq.uop := s1_uop 119 io.lsq.sqIdx := s1_uop.sqIdx 120 io.lsq.mask := s1_mask 121 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 122 123 io.out.valid := io.in.valid && !s1_tlb_miss 124 io.out.bits.paddr := s1_paddr 125 io.out.bits.mmio := s1_mmio 126 io.out.bits.tlbMiss := s1_tlb_miss 127 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 128 129 io.in.ready := !io.in.valid || io.out.ready 130 131} 132 133 134// Load Pipeline Stage 2 135// DCache resp 136class LoadUnit_S2 extends XSModule { 137 val io = IO(new Bundle() { 138 val in = Flipped(Decoupled(new LsPipelineBundle)) 139 val out = Decoupled(new LsPipelineBundle) 140 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 141 val lsq = new LoadForwardQueryIO 142 val sbuffer = new LoadForwardQueryIO 143 }) 144 145 val s2_uop = io.in.bits.uop 146 val s2_mask = io.in.bits.mask 147 val s2_paddr = io.in.bits.paddr 148 val s2_cache_miss = io.dcacheResp.bits.miss 149 val s2_cache_nack = io.dcacheResp.bits.nack 150 151 152 io.dcacheResp.ready := true.B 153 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 154 155 val forwardMask = io.out.bits.forwardMask 156 val forwardData = io.out.bits.forwardData 157 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 158 159 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 160 s2_uop.cf.pc, 161 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 162 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 163 ) 164 165 // data merge 166 val rdata = VecInit((0 until XLEN / 8).map(j => 167 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 168 val rdataSel = LookupTree(s2_paddr(2, 0), List( 169 "b000".U -> rdata(63, 0), 170 "b001".U -> rdata(63, 8), 171 "b010".U -> rdata(63, 16), 172 "b011".U -> rdata(63, 24), 173 "b100".U -> rdata(63, 32), 174 "b101".U -> rdata(63, 40), 175 "b110".U -> rdata(63, 48), 176 "b111".U -> rdata(63, 56) 177 )) 178 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 179 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 180 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 181 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 182 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 183 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 184 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 185 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN), 186 LSUOpType.flw -> boxF32ToF64(rdataSel(31, 0)) 187 )) 188 189 // TODO: ECC check 190 191 io.out.valid := io.in.valid 192 // Inst will be canceled in store queue / lsq, 193 // so we do not need to care about flush in load / store unit's out.valid 194 io.out.bits := io.in.bits 195 io.out.bits.data := rdataPartialLoad 196 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 197 io.out.bits.mmio := io.in.bits.mmio 198 199 io.in.ready := io.out.ready || !io.in.valid 200 201 // merge forward result 202 // lsq has higher priority than sbuffer 203 io.lsq := DontCare 204 io.sbuffer := DontCare 205 // generate XLEN/8 Muxs 206 for (i <- 0 until XLEN / 8) { 207 when (io.sbuffer.forwardMask(i)) { 208 io.out.bits.forwardMask(i) := true.B 209 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 210 } 211 when (io.lsq.forwardMask(i)) { 212 io.out.bits.forwardMask(i) := true.B 213 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 214 } 215 } 216 217 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 218 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 219 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 220 ) 221 222} 223 224class LoadUnit extends XSModule { 225 val io = IO(new Bundle() { 226 val ldin = Flipped(Decoupled(new ExuInput)) 227 val ldout = Decoupled(new ExuOutput) 228 val redirect = Flipped(ValidIO(new Redirect)) 229 val tlbFeedback = ValidIO(new TlbFeedback) 230 val dcache = new DCacheLoadIO 231 val dtlb = new TlbRequestIO() 232 val sbuffer = new LoadForwardQueryIO 233 val lsq = new LoadToLsqIO 234 }) 235 236 val load_s0 = Module(new LoadUnit_S0) 237 val load_s1 = Module(new LoadUnit_S1) 238 val load_s2 = Module(new LoadUnit_S2) 239 240 load_s0.io.in <> io.ldin 241 load_s0.io.dtlbReq <> io.dtlb.req 242 load_s0.io.dcacheReq <> io.dcache.req 243 244 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 245 246 load_s1.io.dtlbResp <> io.dtlb.resp 247 load_s1.io.tlbFeedback <> io.tlbFeedback 248 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 249 io.dcache.s1_kill := DontCare // FIXME 250 load_s1.io.sbuffer <> io.sbuffer 251 load_s1.io.lsq <> io.lsq.forward 252 253 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 254 255 load_s2.io.dcacheResp <> io.dcache.resp 256 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 257 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 258 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 259 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 260 261 XSDebug(load_s0.io.out.valid, 262 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 263 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 264 XSDebug(load_s1.io.out.valid, 265 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 266 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 267 268 // writeback to LSQ 269 // Current dcache use MSHR 270 io.lsq.loadIn.valid := load_s2.io.out.valid 271 io.lsq.loadIn.bits := load_s2.io.out.bits 272 273 val hitLoadOut = Wire(Valid(new ExuOutput)) 274 hitLoadOut.valid := load_s2.io.out.valid && (!load_s2.io.out.bits.miss || load_s2.io.out.bits.uop.cf.exceptionVec.asUInt.orR) 275 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 276 hitLoadOut.bits.data := load_s2.io.out.bits.data 277 hitLoadOut.bits.redirectValid := false.B 278 hitLoadOut.bits.redirect := DontCare 279 hitLoadOut.bits.brUpdate := DontCare 280 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 281 hitLoadOut.bits.fflags := DontCare 282 283 // TODO: arbiter 284 // if hit, writeback result to CDB 285 // val ldout = Vec(2, Decoupled(new ExuOutput)) 286 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 287 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 288 // io.ldout <> cdbArb.io.out 289 // hitLoadOut <> cdbArb.io.in(0) 290 // io.lsq.ldout <> cdbArb.io.in(1) // missLoadOut 291 load_s2.io.out.ready := true.B 292 io.lsq.ldout.ready := !hitLoadOut.valid 293 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 294 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 295 296 when(io.ldout.fire()){ 297 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 298 } 299}