1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TLB, TlbCmd, TlbPtwIO, TlbReq, TlbRequestIO, TlbResp} 28 29class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 30 val loadIn = ValidIO(new LsPipelineBundle) 31 val ldout = Flipped(DecoupledIO(new ExuOutput)) 32 val loadDataForwarded = Output(Bool()) 33 val needReplayFromRS = Output(Bool()) 34 val forward = new PipeLoadForwardQueryIO 35 val loadViolationQuery = new LoadViolationQueryIO 36} 37 38class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 39 // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 40 val data = UInt(XLEN.W) 41 val valid = Bool() 42} 43 44// Load Pipeline Stage 0 45// Generate addr, use addr to query DCache and DTLB 46class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParameters{ 47 val io = IO(new Bundle() { 48 val in = Flipped(Decoupled(new ExuInput)) 49 val out = Decoupled(new LsPipelineBundle) 50 val fastpath = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 51 val dtlbReq = DecoupledIO(new TlbReq) 52 val dcacheReq = DecoupledIO(new DCacheWordReq) 53 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 54 val isFirstIssue = Input(Bool()) 55 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 56 }) 57 require(LoadPipelineWidth == exuParameters.LduCnt) 58 59 val s0_uop = io.in.bits.uop 60 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 61 62 val s0_vaddr = WireInit(io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits)) 63 val s0_mask = WireInit(genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0))) 64 65 if (EnableLoadToLoadForward) { 66 // slow vaddr from non-load insts 67 val slowpath_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 68 val slowpath_mask = genWmask(slowpath_vaddr, s0_uop.ctrl.fuOpType(1,0)) 69 70 // fast vaddr from load insts 71 val fastpath_vaddrs = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 72 io.fastpath(i).data + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 73 }))) 74 val fastpath_masks = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 75 genWmask(fastpath_vaddrs(i), s0_uop.ctrl.fuOpType(1,0)) 76 }))) 77 val fastpath_vaddr = Mux1H(io.loadFastMatch, fastpath_vaddrs) 78 val fastpath_mask = Mux1H(io.loadFastMatch, fastpath_masks) 79 80 // select vaddr from 2 alus 81 s0_vaddr := Mux(io.loadFastMatch.orR, fastpath_vaddr, slowpath_vaddr) 82 s0_mask := Mux(io.loadFastMatch.orR, fastpath_mask, slowpath_mask) 83 XSPerfAccumulate("load_to_load_forward", io.loadFastMatch.orR && io.in.fire()) 84 } 85 86 val isSoftPrefetch = LSUOpType.isPrefetch(s0_uop.ctrl.fuOpType) 87 val isSoftPrefetchRead = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_r 88 val isSoftPrefetchWrite = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_w 89 90 // query DTLB 91 io.dtlbReq.valid := io.in.valid 92 io.dtlbReq.bits.vaddr := s0_vaddr 93 io.dtlbReq.bits.cmd := TlbCmd.read 94 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 95 io.dtlbReq.bits.robIdx := s0_uop.robIdx 96 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 97 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 98 99 // query DCache 100 io.dcacheReq.valid := io.in.valid 101 when (isSoftPrefetchRead) { 102 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFR 103 }.elsewhen (isSoftPrefetchWrite) { 104 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFW 105 }.otherwise { 106 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 107 } 108 io.dcacheReq.bits.addr := s0_vaddr 109 io.dcacheReq.bits.mask := s0_mask 110 io.dcacheReq.bits.data := DontCare 111 when(isSoftPrefetch) { 112 io.dcacheReq.bits.instrtype := SOFT_PREFETCH.U 113 }.otherwise { 114 io.dcacheReq.bits.instrtype := LOAD_SOURCE.U 115 } 116 117 // TODO: update cache meta 118 io.dcacheReq.bits.id := DontCare 119 120 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 121 "b00".U -> true.B, //b 122 "b01".U -> (s0_vaddr(0) === 0.U), //h 123 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 124 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 125 )) 126 127 io.out.valid := io.in.valid && io.dcacheReq.ready 128 129 io.out.bits := DontCare 130 io.out.bits.vaddr := s0_vaddr 131 io.out.bits.mask := s0_mask 132 io.out.bits.uop := s0_uop 133 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 134 io.out.bits.rsIdx := io.rsIdx 135 io.out.bits.isFirstIssue := io.isFirstIssue 136 io.out.bits.isSoftPrefetch := isSoftPrefetch 137 138 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 139 140 XSDebug(io.dcacheReq.fire(), 141 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 142 ) 143 XSPerfAccumulate("in_valid", io.in.valid) 144 XSPerfAccumulate("in_fire", io.in.fire) 145 XSPerfAccumulate("in_fire_first_issue", io.in.valid && io.isFirstIssue) 146 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 147 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 148 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 149 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 150 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 151 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 152} 153 154 155// Load Pipeline Stage 1 156// TLB resp (send paddr to dcache) 157class LoadUnit_S1(implicit p: Parameters) extends XSModule { 158 val io = IO(new Bundle() { 159 val in = Flipped(Decoupled(new LsPipelineBundle)) 160 val out = Decoupled(new LsPipelineBundle) 161 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 162 val dcachePAddr = Output(UInt(PAddrBits.W)) 163 val dcacheKill = Output(Bool()) 164 val fastUopKill = Output(Bool()) 165 val dcacheBankConflict = Input(Bool()) 166 val fullForwardFast = Output(Bool()) 167 val sbuffer = new LoadForwardQueryIO 168 val lsq = new PipeLoadForwardQueryIO 169 val loadViolationQueryReq = Decoupled(new LoadViolationQueryReq) 170 val rsFeedback = ValidIO(new RSFeedback) 171 val csrCtrl = Flipped(new CustomCSRCtrlIO) 172 val needLdVioCheckRedo = Output(Bool()) 173 }) 174 175 val s1_uop = io.in.bits.uop 176 val s1_paddr = io.dtlbResp.bits.paddr 177 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR // af & pf exception were modified below. 178 val s1_tlb_miss = io.dtlbResp.bits.miss 179 val s1_mask = io.in.bits.mask 180 val s1_bank_conflict = io.dcacheBankConflict 181 182 io.out.bits := io.in.bits // forwardXX field will be updated in s1 183 184 io.dtlbResp.ready := true.B 185 186 // TOOD: PMA check 187 io.dcachePAddr := s1_paddr 188 //io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 189 io.dcacheKill := s1_tlb_miss || s1_exception 190 io.fastUopKill := io.dtlbResp.bits.fast_miss || s1_exception 191 192 // load forward query datapath 193 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 194 io.sbuffer.vaddr := io.in.bits.vaddr 195 io.sbuffer.paddr := s1_paddr 196 io.sbuffer.uop := s1_uop 197 io.sbuffer.sqIdx := s1_uop.sqIdx 198 io.sbuffer.mask := s1_mask 199 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 200 201 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 202 io.lsq.vaddr := io.in.bits.vaddr 203 io.lsq.paddr := s1_paddr 204 io.lsq.uop := s1_uop 205 io.lsq.sqIdx := s1_uop.sqIdx 206 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 207 io.lsq.mask := s1_mask 208 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 209 210 // ld-ld violation query 211 io.loadViolationQueryReq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 212 io.loadViolationQueryReq.bits.paddr := s1_paddr 213 io.loadViolationQueryReq.bits.uop := s1_uop 214 215 // Generate forwardMaskFast to wake up insts earlier 216 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 217 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 218 219 // Generate feedback signal caused by: 220 // * dcache bank conflict 221 // * need redo ld-ld violation check 222 val needLdVioCheckRedo = io.loadViolationQueryReq.valid && 223 !io.loadViolationQueryReq.ready && 224 RegNext(io.csrCtrl.ldld_vio_check) 225 io.needLdVioCheckRedo := needLdVioCheckRedo 226 io.rsFeedback.valid := io.in.valid && (s1_bank_conflict || needLdVioCheckRedo) 227 io.rsFeedback.bits.hit := false.B // we have found s1_bank_conflict / re do ld-ld violation check 228 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 229 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 230 io.rsFeedback.bits.sourceType := Mux(s1_bank_conflict, RSFeedbackType.bankConflict, RSFeedbackType.ldVioCheckRedo) 231 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 232 233 // if replay is detected in load_s1, 234 // load inst will be canceled immediately 235 io.out.valid := io.in.valid && !io.rsFeedback.valid 236 io.out.bits.paddr := s1_paddr 237 io.out.bits.tlbMiss := s1_tlb_miss 238 239 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 240 // af & pf exception were modified 241 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 242 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 243 244 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 245 io.out.bits.rsIdx := io.in.bits.rsIdx 246 247 io.out.bits.isSoftPrefetch := io.in.bits.isSoftPrefetch 248 249 io.in.ready := !io.in.valid || io.out.ready 250 251 XSPerfAccumulate("in_valid", io.in.valid) 252 XSPerfAccumulate("in_fire", io.in.fire) 253 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 254 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 255 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 256 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 257} 258 259// Load Pipeline Stage 2 260// DCache resp 261class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 262 val io = IO(new Bundle() { 263 val in = Flipped(Decoupled(new LsPipelineBundle)) 264 val out = Decoupled(new LsPipelineBundle) 265 val rsFeedback = ValidIO(new RSFeedback) 266 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 267 val pmpResp = Flipped(new PMPRespBundle()) 268 val lsq = new LoadForwardQueryIO 269 val dataInvalidSqIdx = Input(UInt()) 270 val sbuffer = new LoadForwardQueryIO 271 val dataForwarded = Output(Bool()) 272 val needReplayFromRS = Output(Bool()) 273 val fullForward = Output(Bool()) 274 val fastpath = Output(new LoadToLoadIO) 275 val dcache_kill = Output(Bool()) 276 val loadViolationQueryResp = Flipped(Valid(new LoadViolationQueryResp)) 277 val csrCtrl = Flipped(new CustomCSRCtrlIO) 278 val sentFastUop = Input(Bool()) 279 }) 280 val isSoftPrefetch = io.in.bits.isSoftPrefetch 281 val excep = WireInit(io.in.bits.uop.cf.exceptionVec) 282 excep(loadAccessFault) := io.in.bits.uop.cf.exceptionVec(loadAccessFault) || io.pmpResp.ld 283 when (isSoftPrefetch) { 284 excep := 0.U.asTypeOf(excep.cloneType) 285 } 286 val s2_exception = selectLoad(excep, false).asUInt.orR 287 288 val actually_mmio = io.pmpResp.mmio 289 val s2_uop = io.in.bits.uop 290 val s2_mask = io.in.bits.mask 291 val s2_paddr = io.in.bits.paddr 292 val s2_tlb_miss = io.in.bits.tlbMiss 293 val s2_data_invalid = io.lsq.dataInvalid 294 val s2_mmio = !isSoftPrefetch && actually_mmio && !s2_exception 295 val s2_cache_miss = io.dcacheResp.bits.miss 296 val s2_cache_replay = io.dcacheResp.bits.replay 297 val s2_is_prefetch = io.in.bits.isSoftPrefetch 298 299 // val cnt = RegInit(127.U) 300 // cnt := cnt + io.in.valid.asUInt 301 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 302 303 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 304 // assert(!s2_forward_fail) 305 io.dcache_kill := false.B // move pmp resp kill to outside 306 io.dcacheResp.ready := true.B 307 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio || s2_is_prefetch) 308 assert(!(io.in.valid && (dcacheShouldResp && !io.dcacheResp.valid)), "DCache response got lost") 309 310 // merge forward result 311 // lsq has higher priority than sbuffer 312 val forwardMask = Wire(Vec(8, Bool())) 313 val forwardData = Wire(Vec(8, UInt(8.W))) 314 315 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 316 io.lsq := DontCare 317 io.sbuffer := DontCare 318 io.fullForward := fullForward 319 320 // generate XLEN/8 Muxs 321 for (i <- 0 until XLEN / 8) { 322 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 323 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 324 } 325 326 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 327 s2_uop.cf.pc, 328 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 329 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 330 ) 331 332 // data merge 333 val rdataVec = VecInit((0 until XLEN / 8).map(j => 334 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 335 val rdata = rdataVec.asUInt 336 val rdataSel = LookupTree(s2_paddr(2, 0), List( 337 "b000".U -> rdata(63, 0), 338 "b001".U -> rdata(63, 8), 339 "b010".U -> rdata(63, 16), 340 "b011".U -> rdata(63, 24), 341 "b100".U -> rdata(63, 32), 342 "b101".U -> rdata(63, 40), 343 "b110".U -> rdata(63, 48), 344 "b111".U -> rdata(63, 56) 345 )) 346 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 347 348 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 349 // Inst will be canceled in store queue / lsq, 350 // so we do not need to care about flush in load / store unit's out.valid 351 io.out.bits := io.in.bits 352 io.out.bits.data := rdataPartialLoad 353 // when exception occurs, set it to not miss and let it write back to rob (via int port) 354 if (EnableFastForward) { 355 io.out.bits.miss := s2_cache_miss && 356 !s2_exception && 357 !s2_forward_fail && 358 !fullForward && 359 !s2_is_prefetch 360 } else { 361 io.out.bits.miss := s2_cache_miss && 362 !s2_exception && 363 !s2_forward_fail && 364 !s2_is_prefetch 365 } 366 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 367 // if forward fail, replay this inst from fetch 368 val forwardFailReplay = s2_forward_fail && !s2_mmio 369 // if ld-ld violation is detected, replay from this inst from fetch 370 val ldldVioReplay = io.loadViolationQueryResp.valid && 371 io.loadViolationQueryResp.bits.have_violation && 372 RegNext(io.csrCtrl.ldld_vio_check) 373 io.out.bits.uop.ctrl.replayInst := forwardFailReplay || ldldVioReplay 374 io.out.bits.mmio := s2_mmio 375 io.out.bits.uop.ctrl.flushPipe := io.in.bits.uop.ctrl.flushPipe || (s2_mmio && io.sentFastUop) 376 io.out.bits.uop.cf.exceptionVec := excep 377 378 // For timing reasons, sometimes we can not let 379 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 380 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 381 // and dcache query is no longer needed. 382 // Such inst will be writebacked from load queue. 383 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 384 // io.out.bits.forwardX will be send to lq 385 io.out.bits.forwardMask := forwardMask 386 // data retbrived from dcache is also included in io.out.bits.forwardData 387 io.out.bits.forwardData := rdataVec 388 389 io.in.ready := io.out.ready || !io.in.valid 390 391 // feedback tlb result to RS 392 io.rsFeedback.valid := io.in.valid 393 when (io.in.bits.isSoftPrefetch) { 394 io.rsFeedback.bits.hit := (!s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception)) 395 }.otherwise { 396 if (EnableFastForward) { 397 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 398 } else { 399 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) && !s2_data_invalid 400 } 401 } 402 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 403 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 404 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 405 Mux(s2_cache_replay, 406 RSFeedbackType.mshrFull, 407 RSFeedbackType.dataInvalid 408 ) 409 ) 410 io.rsFeedback.bits.dataInvalidSqIdx.value := io.dataInvalidSqIdx 411 io.rsFeedback.bits.dataInvalidSqIdx.flag := DontCare 412 413 // s2_cache_replay is quite slow to generate, send it separately to LQ 414 if (EnableFastForward) { 415 io.needReplayFromRS := s2_cache_replay && !fullForward 416 } else { 417 io.needReplayFromRS := s2_cache_replay 418 } 419 420 // fast load to load forward 421 io.fastpath.valid := io.in.valid // for debug only 422 io.fastpath.data := rdata // raw data 423 424 425 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 426 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 427 forwardData.asUInt, forwardMask.asUInt 428 ) 429 430 XSPerfAccumulate("in_valid", io.in.valid) 431 XSPerfAccumulate("in_fire", io.in.fire) 432 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 433 XSPerfAccumulate("dcache_miss", io.in.fire && s2_cache_miss) 434 XSPerfAccumulate("dcache_miss_first_issue", io.in.fire && s2_cache_miss && io.in.bits.isFirstIssue) 435 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 436 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 437 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 438 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 439 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 440 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 441 XSPerfAccumulate("replay_from_fetch_forward", io.out.valid && forwardFailReplay) 442 XSPerfAccumulate("replay_from_fetch_load_vio", io.out.valid && ldldVioReplay) 443} 444 445class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper { 446 val io = IO(new Bundle() { 447 val ldin = Flipped(Decoupled(new ExuInput)) 448 val ldout = Decoupled(new ExuOutput) 449 val redirect = Flipped(ValidIO(new Redirect)) 450 val feedbackSlow = ValidIO(new RSFeedback) 451 val feedbackFast = ValidIO(new RSFeedback) 452 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 453 val isFirstIssue = Input(Bool()) 454 val dcache = new DCacheLoadIO 455 val sbuffer = new LoadForwardQueryIO 456 val lsq = new LoadToLsqIO 457 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 458 459 val tlb = new TlbRequestIO 460 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 461 462 val fastpathOut = Output(new LoadToLoadIO) 463 val fastpathIn = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 464 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 465 466 val csrCtrl = Flipped(new CustomCSRCtrlIO) 467 }) 468 469 val load_s0 = Module(new LoadUnit_S0) 470 val load_s1 = Module(new LoadUnit_S1) 471 val load_s2 = Module(new LoadUnit_S2) 472 473 load_s0.io.in <> io.ldin 474 load_s0.io.dtlbReq <> io.tlb.req 475 load_s0.io.dcacheReq <> io.dcache.req 476 load_s0.io.rsIdx := io.rsIdx 477 load_s0.io.isFirstIssue := io.isFirstIssue 478 load_s0.io.fastpath := io.fastpathIn 479 load_s0.io.loadFastMatch := io.loadFastMatch 480 481 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 482 483 load_s1.io.dtlbResp <> io.tlb.resp 484 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 485 io.dcache.s1_kill <> load_s1.io.dcacheKill 486 load_s1.io.sbuffer <> io.sbuffer 487 load_s1.io.lsq <> io.lsq.forward 488 load_s1.io.loadViolationQueryReq <> io.lsq.loadViolationQuery.req 489 load_s1.io.dcacheBankConflict <> io.dcache.s1_bank_conflict 490 load_s1.io.csrCtrl <> io.csrCtrl 491 492 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 493 494 io.dcache.s2_kill := load_s2.io.dcache_kill || (io.pmp.ld || io.pmp.mmio) // to kill mmio resp which are redirected 495 load_s2.io.dcacheResp <> io.dcache.resp 496 load_s2.io.pmpResp <> io.pmp 497 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 498 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 499 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 500 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 501 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 502 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 503 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 504 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 505 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 506 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 507 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 508 load_s2.io.fastpath <> io.fastpathOut 509 load_s2.io.dataInvalidSqIdx := io.lsq.forward.dataInvalidSqIdx // provide dataInvalidSqIdx to make wakeup faster 510 load_s2.io.loadViolationQueryResp <> io.lsq.loadViolationQuery.resp 511 load_s2.io.csrCtrl <> io.csrCtrl 512 load_s2.io.sentFastUop := RegEnable(io.fastUop.valid, load_s1.io.out.fire()) // RegNext is also ok 513 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 514 515 // feedback tlb miss / dcache miss queue full 516 io.feedbackSlow.bits := RegNext(load_s2.io.rsFeedback.bits) 517 io.feedbackSlow.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 518 519 // feedback bank conflict to rs 520 io.feedbackFast.bits := load_s1.io.rsFeedback.bits 521 io.feedbackFast.valid := load_s1.io.rsFeedback.valid 522 // If replay is reported at load_s1, inst will be canceled (will not enter load_s2), 523 // in that case: 524 // * replay should not be reported twice 525 assert(!(RegNext(RegNext(io.feedbackFast.valid)) && io.feedbackSlow.valid)) 526 // * io.fastUop.valid should not be reported 527 assert(!RegNext(io.feedbackFast.valid && io.fastUop.valid)) 528 529 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 530 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 531 io.lsq.forward.sqIdxMask := sqIdxMaskReg 532 533 // // use s2_hit_way to select data received in s1 534 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 535 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 536 537 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 538 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 539 load_s1.io.in.valid && // valid laod request 540 !load_s1.io.fastUopKill && // not mmio or tlb miss 541 !io.lsq.forward.dataInvalidFast && // forward failed 542 !load_s1.io.needLdVioCheckRedo // load-load violation check: load paddr cam struct hazard 543 io.fastUop.bits := load_s1.io.out.bits.uop 544 545 XSDebug(load_s0.io.out.valid, 546 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 547 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 548 XSDebug(load_s1.io.out.valid, 549 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 550 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 551 552 // writeback to LSQ 553 // Current dcache use MSHR 554 // Load queue will be updated at s2 for both hit/miss int/fp load 555 io.lsq.loadIn.valid := load_s2.io.out.valid 556 io.lsq.loadIn.bits := load_s2.io.out.bits 557 558 // write to rob and writeback bus 559 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 560 561 // Int load, if hit, will be writebacked at s2 562 val hitLoadOut = Wire(Valid(new ExuOutput)) 563 hitLoadOut.valid := s2_wb_valid 564 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 565 hitLoadOut.bits.data := load_s2.io.out.bits.data 566 hitLoadOut.bits.redirectValid := false.B 567 hitLoadOut.bits.redirect := DontCare 568 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 569 hitLoadOut.bits.debug.isPerfCnt := false.B 570 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 571 hitLoadOut.bits.debug.vaddr := load_s2.io.out.bits.vaddr 572 hitLoadOut.bits.fflags := DontCare 573 574 load_s2.io.out.ready := true.B 575 576 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 577 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 578 579 io.lsq.ldout.ready := !hitLoadOut.valid 580 581 val perfinfo = IO(new Bundle(){ 582 val perfEvents = Output(new PerfEventsBundle(12)) 583 }) 584 585 val perfEvents = Seq( 586 ("load_s0_in_fire ", load_s0.io.in.fire() ), 587 ("load_to_load_forward ", load_s0.io.loadFastMatch.orR && load_s0.io.in.fire() ), 588 ("stall_dcache ", load_s0.io.out.valid && load_s0.io.out.ready && !load_s0.io.dcacheReq.ready ), 589 ("addr_spec_success ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) === load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 590 ("addr_spec_failed ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) =/= load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 591 ("load_s1_in_fire ", load_s1.io.in.fire ), 592 ("load_s1_tlb_miss ", load_s1.io.in.fire && load_s1.io.dtlbResp.bits.miss ), 593 ("load_s2_in_fire ", load_s2.io.in.fire ), 594 ("load_s2_dcache_miss ", load_s2.io.in.fire && load_s2.io.dcacheResp.bits.miss ), 595 ("load_s2_replay ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit ), 596 ("load_s2_replay_tlb_miss ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && load_s2.io.in.bits.tlbMiss ), 597 ("load_s2_replay_cache ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && !load_s2.io.in.bits.tlbMiss && load_s2.io.dcacheResp.bits.miss), 598 ) 599 600 for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) { 601 perf_out.incr_step := RegNext(perf) 602 } 603 604 when(io.ldout.fire()){ 605 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 606 } 607} 608