1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10 11class LoadToLsqIO extends XSBundle { 12 val loadIn = ValidIO(new LsPipelineBundle) 13 val ldout = Flipped(DecoupledIO(new ExuOutput)) 14 val forward = new LoadForwardQueryIO 15} 16 17// Load Pipeline Stage 0 18// Generate addr, use addr to query DCache and DTLB 19class LoadUnit_S0 extends XSModule { 20 val io = IO(new Bundle() { 21 val in = Flipped(Decoupled(new ExuInput)) 22 val out = Decoupled(new LsPipelineBundle) 23 val dtlbReq = DecoupledIO(new TlbReq) 24 val dcacheReq = DecoupledIO(new DCacheLoadReq) 25 }) 26 27 val s0_uop = io.in.bits.uop 28 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 29 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 30 31 // query DTLB 32 io.dtlbReq.valid := io.in.valid 33 io.dtlbReq.bits.vaddr := s0_vaddr 34 io.dtlbReq.bits.cmd := TlbCmd.read 35 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 36 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 37 38 // query DCache 39 io.dcacheReq.valid := io.in.valid 40 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 41 io.dcacheReq.bits.addr := s0_vaddr 42 io.dcacheReq.bits.mask := s0_mask 43 io.dcacheReq.bits.data := DontCare 44 45 // TODO: update cache meta 46 io.dcacheReq.bits.meta.id := DontCare 47 io.dcacheReq.bits.meta.vaddr := s0_vaddr 48 io.dcacheReq.bits.meta.paddr := DontCare 49 io.dcacheReq.bits.meta.uop := s0_uop 50 io.dcacheReq.bits.meta.mmio := false.B 51 io.dcacheReq.bits.meta.tlb_miss := false.B 52 io.dcacheReq.bits.meta.mask := s0_mask 53 io.dcacheReq.bits.meta.replay := false.B 54 55 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 56 "b00".U -> true.B, //b 57 "b01".U -> (s0_vaddr(0) === 0.U), //h 58 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 59 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 60 )) 61 62 io.out.valid := io.in.valid && io.dcacheReq.ready 63 64 io.out.bits := DontCare 65 io.out.bits.vaddr := s0_vaddr 66 io.out.bits.mask := s0_mask 67 io.out.bits.uop := s0_uop 68 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 69 70 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 71 72 XSDebug(io.dcacheReq.fire(), 73 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 74 ) 75} 76 77 78// Load Pipeline Stage 1 79// TLB resp (send paddr to dcache) 80class LoadUnit_S1 extends XSModule { 81 val io = IO(new Bundle() { 82 val in = Flipped(Decoupled(new LsPipelineBundle)) 83 val out = Decoupled(new LsPipelineBundle) 84 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 85 val tlbFeedback = ValidIO(new TlbFeedback) 86 val dcachePAddr = Output(UInt(PAddrBits.W)) 87 val sbuffer = new LoadForwardQueryIO 88 val lsq = new LoadForwardQueryIO 89 }) 90 91 val s1_uop = io.in.bits.uop 92 val s1_paddr = io.dtlbResp.bits.paddr 93 val s1_tlb_miss = io.dtlbResp.bits.miss 94 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) && !io.out.bits.uop.cf.exceptionVec.asUInt.orR 95 val s1_mask = io.in.bits.mask 96 97 io.out.bits := io.in.bits // forwardXX field will be updated in s1 98 99 io.dtlbResp.ready := true.B 100 // feedback tlb result to RS 101 io.tlbFeedback.valid := io.in.valid 102 io.tlbFeedback.bits.hit := !s1_tlb_miss 103 io.tlbFeedback.bits.roqIdx := s1_uop.roqIdx 104 105 io.dcachePAddr := s1_paddr 106 107 // load forward query datapath 108 io.sbuffer.valid := io.in.valid 109 io.sbuffer.paddr := s1_paddr 110 io.sbuffer.uop := s1_uop 111 io.sbuffer.sqIdx := s1_uop.sqIdx 112 io.sbuffer.mask := s1_mask 113 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 114 115 io.lsq.valid := io.in.valid 116 io.lsq.paddr := s1_paddr 117 io.lsq.uop := s1_uop 118 io.lsq.sqIdx := s1_uop.sqIdx 119 io.lsq.mask := s1_mask 120 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 121 122 io.out.valid := io.in.valid && !s1_tlb_miss 123 io.out.bits.paddr := s1_paddr 124 io.out.bits.mmio := s1_mmio 125 io.out.bits.tlbMiss := s1_tlb_miss 126 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 127 128 io.in.ready := !io.in.valid || io.out.ready 129 130} 131 132 133// Load Pipeline Stage 2 134// DCache resp 135class LoadUnit_S2 extends XSModule with HasLoadHelper { 136 val io = IO(new Bundle() { 137 val in = Flipped(Decoupled(new LsPipelineBundle)) 138 val out = Decoupled(new LsPipelineBundle) 139 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 140 val lsq = new LoadForwardQueryIO 141 val sbuffer = new LoadForwardQueryIO 142 }) 143 144 val s2_uop = io.in.bits.uop 145 val s2_mask = io.in.bits.mask 146 val s2_paddr = io.in.bits.paddr 147 val s2_cache_miss = io.dcacheResp.bits.miss 148 val s2_cache_nack = io.dcacheResp.bits.nack 149 150 151 io.dcacheResp.ready := true.B 152 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 153 154 val forwardMask = io.out.bits.forwardMask 155 val forwardData = io.out.bits.forwardData 156 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 157 158 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 159 s2_uop.cf.pc, 160 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 161 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 162 ) 163 164 // data merge 165 val rdata = VecInit((0 until XLEN / 8).map(j => 166 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 167 val rdataSel = LookupTree(s2_paddr(2, 0), List( 168 "b000".U -> rdata(63, 0), 169 "b001".U -> rdata(63, 8), 170 "b010".U -> rdata(63, 16), 171 "b011".U -> rdata(63, 24), 172 "b100".U -> rdata(63, 32), 173 "b101".U -> rdata(63, 40), 174 "b110".U -> rdata(63, 48), 175 "b111".U -> rdata(63, 56) 176 )) 177 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 178 179 // TODO: ECC check 180 181 io.out.valid := io.in.valid 182 // Inst will be canceled in store queue / lsq, 183 // so we do not need to care about flush in load / store unit's out.valid 184 io.out.bits := io.in.bits 185 io.out.bits.data := rdataPartialLoad 186 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 187 io.out.bits.mmio := io.in.bits.mmio 188 189 io.in.ready := io.out.ready || !io.in.valid 190 191 // merge forward result 192 // lsq has higher priority than sbuffer 193 io.lsq := DontCare 194 io.sbuffer := DontCare 195 // generate XLEN/8 Muxs 196 for (i <- 0 until XLEN / 8) { 197 when (io.sbuffer.forwardMask(i)) { 198 io.out.bits.forwardMask(i) := true.B 199 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 200 } 201 when (io.lsq.forwardMask(i)) { 202 io.out.bits.forwardMask(i) := true.B 203 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 204 } 205 } 206 207 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 208 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 209 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 210 ) 211} 212 213class LoadUnit extends XSModule with HasLoadHelper { 214 val io = IO(new Bundle() { 215 val ldin = Flipped(Decoupled(new ExuInput)) 216 val ldout = Decoupled(new ExuOutput) 217 val fpout = Decoupled(new ExuOutput) 218 val redirect = Flipped(ValidIO(new Redirect)) 219 val tlbFeedback = ValidIO(new TlbFeedback) 220 val dcache = new DCacheLoadIO 221 val dtlb = new TlbRequestIO() 222 val sbuffer = new LoadForwardQueryIO 223 val lsq = new LoadToLsqIO 224 }) 225 226 val load_s0 = Module(new LoadUnit_S0) 227 val load_s1 = Module(new LoadUnit_S1) 228 val load_s2 = Module(new LoadUnit_S2) 229 230 load_s0.io.in <> io.ldin 231 load_s0.io.dtlbReq <> io.dtlb.req 232 load_s0.io.dcacheReq <> io.dcache.req 233 234 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 235 236 load_s1.io.dtlbResp <> io.dtlb.resp 237 load_s1.io.tlbFeedback <> io.tlbFeedback 238 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 239 io.dcache.s1_kill := DontCare // FIXME 240 load_s1.io.sbuffer <> io.sbuffer 241 load_s1.io.lsq <> io.lsq.forward 242 243 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 244 245 load_s2.io.dcacheResp <> io.dcache.resp 246 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 247 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 248 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 249 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 250 251 XSDebug(load_s0.io.out.valid, 252 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 253 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 254 XSDebug(load_s1.io.out.valid, 255 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 256 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 257 258 // writeback to LSQ 259 // Current dcache use MSHR 260 // Load queue will be updated at s2 for both hit/miss int/fp load 261 io.lsq.loadIn.valid := load_s2.io.out.valid 262 io.lsq.loadIn.bits := load_s2.io.out.bits 263 val s2Valid = load_s2.io.out.valid && (!load_s2.io.out.bits.miss || load_s2.io.out.bits.uop.cf.exceptionVec.asUInt.orR) 264 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 265 266 // Int load, if hit, will be writebacked at s2 267 val intHitLoadOut = Wire(Valid(new ExuOutput)) 268 intHitLoadOut.valid := s2Valid && !load_s2.io.out.bits.uop.ctrl.fpWen 269 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 270 intHitLoadOut.bits.data := load_s2.io.out.bits.data 271 intHitLoadOut.bits.redirectValid := false.B 272 intHitLoadOut.bits.redirect := DontCare 273 intHitLoadOut.bits.brUpdate := DontCare 274 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 275 intHitLoadOut.bits.fflags := DontCare 276 277 load_s2.io.out.ready := true.B 278 279 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 280 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 281 282 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 283 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 284 fpHitLoadOut.valid := s2Valid && load_s2.io.out.bits.uop.ctrl.fpWen 285 fpHitLoadOut.bits := intHitLoadOut.bits 286 287 val fpLoadOut = Wire(Valid(new ExuOutput)) 288 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 289 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 290 291 val fpLoadOutReg = RegNext(fpLoadOut) 292 io.fpout.bits := fpLoadOutReg.bits 293 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 294 io.fpout.valid := RegNext(fpLoadOut.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 295 296 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 297 298 when(io.ldout.fire()){ 299 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 300 } 301 302 when(io.fpout.fire()){ 303 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 304 } 305}