1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan.ExceptionNO._ 24import xiangshan._ 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 27 28// Store Pipeline Stage 0 29// Generate addr, use addr to query DCache and DTLB 30class StoreUnit_S0(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val in = Flipped(Decoupled(new ExuInput)) 33 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 34 val isFirstIssue = Input(Bool()) 35 val out = Decoupled(new LsPipelineBundle) 36 val dtlbReq = DecoupledIO(new TlbReq) 37 }) 38 39 // send req to dtlb 40 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 41 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 42 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 43 val saddr_hi = Mux(saddr_lo(12), 44 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 46 ) 47 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 48 49 io.dtlbReq.bits.vaddr := saddr 50 io.dtlbReq.valid := io.in.valid 51 io.dtlbReq.bits.cmd := TlbCmd.write 52 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 53 io.dtlbReq.bits.robIdx := io.in.bits.uop.robIdx 54 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 55 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 56 57 io.out.bits := DontCare 58 io.out.bits.vaddr := saddr 59 60 // Now data use its own io 61 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 62 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 63 io.out.bits.uop := io.in.bits.uop 64 io.out.bits.miss := DontCare 65 io.out.bits.rsIdx := io.rsIdx 66 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 67 io.out.bits.isFirstIssue := io.isFirstIssue 68 io.out.bits.wlineflag := io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_zero 69 io.out.valid := io.in.valid 70 io.in.ready := io.out.ready 71 72 // exception check 73 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 74 "b00".U -> true.B, //b 75 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 76 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 77 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 78 )) 79 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 80 81 XSPerfAccumulate("in_valid", io.in.valid) 82 XSPerfAccumulate("in_fire", io.in.fire) 83 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.isFirstIssue) 84 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 85 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 86 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 87 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 88} 89 90// Store Pipeline Stage 1 91// TLB resp (send paddr to dcache) 92class StoreUnit_S1(implicit p: Parameters) extends XSModule { 93 val io = IO(new Bundle() { 94 val in = Flipped(Decoupled(new LsPipelineBundle)) 95 val out = Decoupled(new LsPipelineBundle) 96 val lsq = ValidIO(new LsPipelineBundle()) 97 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 98 val rsFeedback = ValidIO(new RSFeedback) 99 }) 100 101 // mmio cbo decoder 102 val is_mmio_cbo = io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 103 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 104 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_inval 105 106 val s1_paddr = io.dtlbResp.bits.paddr 107 val s1_tlb_miss = io.dtlbResp.bits.miss 108 val s1_mmio = is_mmio_cbo 109 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, staCfg).asUInt.orR 110 111 io.in.ready := true.B 112 113 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 114 115 // Send TLB feedback to store issue queue 116 io.rsFeedback.valid := io.in.valid 117 io.rsFeedback.bits.hit := !s1_tlb_miss 118 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 119 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 120 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 121 XSDebug(io.rsFeedback.valid, 122 "S1 Store: tlbHit: %d robIdx: %d\n", 123 io.rsFeedback.bits.hit, 124 io.rsFeedback.bits.rsIdx 125 ) 126 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 127 128 // get paddr from dtlb, check if rollback is needed 129 // writeback store inst to lsq 130 io.out.valid := io.in.valid && !s1_tlb_miss 131 io.out.bits := io.in.bits 132 io.out.bits.paddr := s1_paddr 133 io.out.bits.miss := false.B 134 io.out.bits.mmio := s1_mmio 135 io.out.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 136 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 137 138 io.lsq.valid := io.in.valid 139 io.lsq.bits := io.out.bits 140 io.lsq.bits.miss := s1_tlb_miss 141 142 // mmio inst with exception will be writebacked immediately 143 // io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 144 145 XSPerfAccumulate("in_valid", io.in.valid) 146 XSPerfAccumulate("in_fire", io.in.fire) 147 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 148 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 149 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 150} 151 152class StoreUnit_S2(implicit p: Parameters) extends XSModule { 153 val io = IO(new Bundle() { 154 val in = Flipped(Decoupled(new LsPipelineBundle)) 155 val pmpResp = Flipped(new PMPRespBundle) 156 val out = Decoupled(new LsPipelineBundle) 157 }) 158 159 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, staCfg).asUInt.orR 160 161 io.in.ready := true.B 162 io.out.bits := io.in.bits 163 io.out.bits.mmio := (io.in.bits.mmio || io.pmpResp.mmio) && !s2_exception 164 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.in.bits.uop.cf.exceptionVec(storeAccessFault) || io.pmpResp.st 165 io.out.valid := io.in.valid && (!io.out.bits.mmio || s2_exception) 166} 167 168class StoreUnit_S3(implicit p: Parameters) extends XSModule { 169 val io = IO(new Bundle() { 170 val in = Flipped(Decoupled(new LsPipelineBundle)) 171 val stout = DecoupledIO(new ExuOutput) // writeback store 172 }) 173 174 io.in.ready := true.B 175 176 io.stout.valid := io.in.valid 177 io.stout.bits.uop := io.in.bits.uop 178 io.stout.bits.data := DontCare 179 io.stout.bits.redirectValid := false.B 180 io.stout.bits.redirect := DontCare 181 io.stout.bits.debug.isMMIO := io.in.bits.mmio 182 io.stout.bits.debug.paddr := io.in.bits.paddr 183 io.stout.bits.debug.vaddr := io.in.bits.vaddr 184 io.stout.bits.debug.isPerfCnt := false.B 185 io.stout.bits.fflags := DontCare 186 187} 188 189class StoreUnit(implicit p: Parameters) extends XSModule { 190 val io = IO(new Bundle() { 191 val stin = Flipped(Decoupled(new ExuInput)) 192 val redirect = Flipped(ValidIO(new Redirect)) 193 val feedbackSlow = ValidIO(new RSFeedback) 194 val tlb = new TlbRequestIO() 195 val pmp = Flipped(new PMPRespBundle()) 196 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 197 val isFirstIssue = Input(Bool()) 198 val lsq = ValidIO(new LsPipelineBundle) 199 val lsq_replenish = Output(new LsPipelineBundle()) 200 val stout = DecoupledIO(new ExuOutput) // writeback store 201 }) 202 203 val store_s0 = Module(new StoreUnit_S0) 204 val store_s1 = Module(new StoreUnit_S1) 205 val store_s2 = Module(new StoreUnit_S2) 206 val store_s3 = Module(new StoreUnit_S3) 207 208 store_s0.io.in <> io.stin 209 store_s0.io.dtlbReq <> io.tlb.req 210 store_s0.io.rsIdx := io.rsIdx 211 store_s0.io.isFirstIssue := io.isFirstIssue 212 213 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 214 215 216 store_s1.io.dtlbResp <> io.tlb.resp 217 store_s1.io.rsFeedback <> io.feedbackSlow 218 io.lsq <> store_s1.io.lsq 219 220 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 221 222 store_s2.io.pmpResp <> io.pmp 223 io.lsq_replenish := store_s2.io.out.bits // mmio and exception 224 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 225 226 store_s3.io.stout <> io.stout 227 228 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 229 XSDebug(cond, 230 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 231 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 232 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 233 p"data ${Hexadecimal(pipeline.data)} " + 234 p"mask ${Hexadecimal(pipeline.mask)}\n" 235 ) 236 } 237 238 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 239 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 240} 241