1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.ExceptionNO._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput, connectSamePort} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.backend.fu.NewCSR._ 32import xiangshan.mem.Bundles._ 33import xiangshan.cache.mmu.{Pbmt, TlbCmd, TlbReq, TlbRequestIO, TlbResp} 34import xiangshan.cache.{DCacheStoreIO, DcacheStoreRequestIO, HasDCacheParameters, MemoryOpConstants, StorePrefetchReq} 35 36class StoreUnit(implicit p: Parameters) extends XSModule 37 with HasDCacheParameters 38 with HasVLSUParameters 39 { 40 val io = IO(new Bundle() { 41 val redirect = Flipped(ValidIO(new Redirect)) 42 val csrCtrl = Flipped(new CustomCSRCtrlIO) 43 val stin = Flipped(Decoupled(new MemExuInput)) 44 val issue = Valid(new MemExuInput) 45 // misalignBuffer issue path 46 val misalign_stin = Flipped(Decoupled(new LsPipelineBundle)) 47 val misalign_stout = Valid(new SqWriteBundle) 48 val tlb = new TlbRequestIO() 49 val dcache = new DCacheStoreIO 50 val pmp = Flipped(new PMPRespBundle()) 51 val lsq = ValidIO(new LsPipelineBundle) 52 val lsq_replenish = Output(new LsPipelineBundle()) 53 val feedback_slow = ValidIO(new RSFeedback) 54 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 55 // provide prefetch info to sms 56 val prefetch_train = ValidIO(new LsPrefetchTrainBundle()) 57 // speculative for gated control 58 val s1_prefetch_spec = Output(Bool()) 59 val s2_prefetch_spec = Output(Bool()) 60 val stld_nuke_query = Valid(new StoreNukeQueryBundle) 61 val stout = DecoupledIO(new MemExuOutput) // writeback store 62 val vecstout = DecoupledIO(new VecPipelineFeedbackIO(isVStore = true)) 63 // store mask, send to sq in store_s0 64 val st_mask_out = Valid(new StoreMaskBundle) 65 val debug_ls = Output(new DebugLsInfoBundle) 66 // vector 67 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 68 val vec_isFirstIssue = Input(Bool()) 69 // writeback to misalign buffer 70 val misalign_buf = Decoupled(new LsPipelineBundle) 71 // trigger 72 val fromCsrTrigger = Input(new CsrTriggerBundle) 73 74 val s0_s1_valid = Output(Bool()) 75 }) 76 77 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 78 79 // Pipeline 80 // -------------------------------------------------------------------------------- 81 // stage 0 82 // -------------------------------------------------------------------------------- 83 // generate addr, use addr to query DCache and DTLB 84 val s0_iss_valid = io.stin.valid 85 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 86 val s0_vec_valid = io.vecstin.valid 87 val s0_ma_st_valid = io.misalign_stin.valid 88 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid || s0_ma_st_valid 89 val s0_use_flow_ma = s0_ma_st_valid 90 val s0_use_flow_vec = s0_vec_valid && !s0_ma_st_valid 91 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 92 val s0_use_flow_prf = s0_prf_valid && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 93 val s0_use_non_prf_flow = s0_use_flow_rs || s0_use_flow_vec || s0_use_flow_ma 94 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 95 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 96 val s0_uop = Mux( 97 s0_use_flow_ma, 98 io.misalign_stin.bits.uop, 99 Mux( 100 s0_use_flow_rs, 101 s0_stin.uop, 102 s0_vecstin.uop 103 ) 104 ) 105 val s0_isFirstIssue = Mux( 106 s0_use_flow_ma, 107 false.B, 108 s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 109 ) 110 val s0_size = Mux(s0_use_non_prf_flow, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 111 val s0_mem_idx = Mux(s0_use_non_prf_flow, s0_uop.sqIdx.value, 0.U) 112 val s0_rob_idx = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 113 val s0_pc = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U) 114 val s0_instr_type = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 115 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 116 val s0_out = Wire(new LsPipelineBundle) 117 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 118 val s0_can_go = s1_ready 119 val s0_fire = s0_valid && !s0_kill && s0_can_go 120 val s0_is128bit = Wire(Bool()) 121 // vector 122 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 123 // val s0_flowPtr = s0_vecstin.flowPtr 124 // val s0_isLastElem = s0_vecstin.isLastElem 125 val s0_secondInv = s0_vecstin.usSecondInv 126 val s0_elemIdx = s0_vecstin.elemIdx 127 val s0_alignedType = s0_vecstin.alignedType 128 val s0_mBIndex = s0_vecstin.mBIndex 129 val s0_vecBaseVaddr = s0_vecstin.basevaddr 130 val s0_isFinalSplit = io.misalign_stin.valid && io.misalign_stin.bits.isFinalSplit 131 132 // generate addr 133 val s0_saddr = s0_stin.src(0) + SignExt(s0_stin.uop.imm(11,0), VAddrBits) 134 val s0_fullva = Wire(UInt(XLEN.W)) 135 136 val s0_vaddr = Mux( 137 s0_use_flow_ma, 138 io.misalign_stin.bits.vaddr, 139 Mux( 140 s0_use_flow_rs, 141 s0_saddr, 142 Mux( 143 s0_use_flow_vec, 144 s0_vecstin.vaddr(VAddrBits - 1, 0), 145 io.prefetch_req.bits.vaddr 146 ) 147 ) 148 ) 149 150 val s0_isCbo = s0_use_flow_rs && LSUOpType.isCboAll(s0_stin.uop.fuOpType) 151 // only simulation 152 val cbo_assert_flag = LSUOpType.isCboAll(s0_out.uop.fuOpType) 153 XSError(!s0_use_flow_rs && cbo_assert_flag && s0_valid, "cbo instruction selection error.") 154 155 val s0_alignType = Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)) 156 // exception check 157 val s0_addr_aligned = LookupTree(s0_alignType, List( 158 "b00".U -> true.B, //b 159 "b01".U -> (s0_vaddr(0) === 0.U), //h 160 "b10".U -> (s0_vaddr(1,0) === 0.U), //w 161 "b11".U -> (s0_vaddr(2,0) === 0.U) //d 162 )) || s0_isCbo 163 // if vector store sends 128-bit requests, its address must be 128-aligned 164 XSError(s0_use_flow_vec && s0_vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 165 166 val s0_isMisalign = Mux(s0_use_non_prf_flow, (!s0_addr_aligned || s0_vecstin.uop.exceptionVec(storeAddrMisaligned) && s0_vecActive), false.B) 167 val s0_addr_low = s0_vaddr(4, 0) 168 val s0_addr_Up_low = LookupTree(s0_alignType, List( 169 "b00".U -> 0.U, 170 "b01".U -> 1.U, 171 "b10".U -> 3.U, 172 "b11".U -> 7.U 173 )) + s0_addr_low 174 val s0_rs_corss16Bytes = s0_addr_Up_low(4) =/= s0_addr_low(4) 175 val s0_misalignWith16Byte = !s0_rs_corss16Bytes && !s0_addr_aligned && !s0_use_flow_prf 176 s0_is128bit := Mux(s0_use_flow_ma, io.misalign_stin.bits.is128bit, is128Bit(s0_vecstin.alignedType) || s0_misalignWith16Byte) 177 178 s0_fullva := Mux( 179 s0_use_flow_rs, 180 s0_stin.src(0) + SignExt(s0_stin.uop.imm(11,0), XLEN), 181 Mux( 182 s0_use_flow_vec, 183 s0_vecstin.vaddr, 184 s0_vaddr 185 ) 186 ) 187 188 val s0_mask = Mux( 189 s0_use_flow_ma, 190 io.misalign_stin.bits.mask, 191 Mux( 192 s0_use_flow_rs, 193 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 194 Mux( 195 s0_use_flow_vec, 196 s0_vecstin.mask, 197 // -1.asSInt.asUInt 198 Fill(VLEN/8, 1.U(1.W)) 199 ) 200 ) 201 ) 202 203 io.tlb.req.valid := s0_valid 204 io.tlb.req.bits.vaddr := s0_vaddr 205 io.tlb.req.bits.fullva := s0_fullva 206 io.tlb.req.bits.checkfullva := s0_use_flow_rs || s0_use_flow_vec 207 io.tlb.req.bits.cmd := TlbCmd.write 208 io.tlb.req.bits.isPrefetch := s0_use_flow_prf 209 io.tlb.req.bits.size := s0_size 210 io.tlb.req.bits.kill := false.B 211 io.tlb.req.bits.memidx.is_ld := false.B 212 io.tlb.req.bits.memidx.is_st := true.B 213 io.tlb.req.bits.memidx.idx := s0_mem_idx 214 io.tlb.req.bits.debug.robIdx := s0_rob_idx 215 io.tlb.req.bits.no_translate := false.B 216 io.tlb.req.bits.debug.pc := s0_pc 217 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 218 io.tlb.req_kill := false.B 219 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_uop.fuOpType) 220 io.tlb.req.bits.hlvx := false.B 221 io.tlb.req.bits.pmp_addr := DontCare 222 223 // Dcache access here: not **real** dcache write 224 // just read meta and tag in dcache, to find out the store will hit or miss 225 226 // NOTE: The store request does not wait for the dcache to be ready. 227 // If the dcache is not ready at this time, the dcache is not queried. 228 // But, store prefetch request will always wait for dcache to be ready to make progress. 229 io.dcache.req.valid := s0_fire 230 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 231 io.dcache.req.bits.vaddr := s0_vaddr 232 io.dcache.req.bits.instrtype := s0_instr_type 233 234 s0_out := DontCare 235 s0_out.vaddr := s0_vaddr 236 s0_out.fullva := s0_fullva 237 // Now data use its own io 238 s0_out.data := s0_stin.src(1) 239 s0_out.uop := s0_uop 240 s0_out.miss := false.B 241 // For unaligned, we need to generate a base-aligned mask in storeunit and then do a shift split in StoreQueue. 242 s0_out.mask := Mux(s0_rs_corss16Bytes && !s0_addr_aligned, genBasemask(s0_saddr,s0_alignType(1,0)), s0_mask) 243 s0_out.isFirstIssue := s0_isFirstIssue 244 s0_out.isHWPrefetch := s0_use_flow_prf 245 s0_out.wlineflag := s0_wlineflag 246 s0_out.isvec := s0_use_flow_vec 247 s0_out.is128bit := s0_is128bit 248 s0_out.vecActive := s0_vecActive 249 s0_out.usSecondInv := s0_secondInv 250 s0_out.elemIdx := s0_elemIdx 251 s0_out.alignedType := s0_alignedType 252 s0_out.mbIndex := s0_mBIndex 253 s0_out.misalignWith16Byte := s0_misalignWith16Byte 254 s0_out.isMisalign := s0_isMisalign 255 s0_out.vecBaseVaddr := s0_vecBaseVaddr 256 when(s0_valid && s0_isFirstIssue) { 257 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 258 } 259 s0_out.isFrmMisAlignBuf := s0_use_flow_ma 260 s0_out.isFinalSplit := s0_isFinalSplit 261// s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_non_prf_flow, (!s0_addr_aligned || s0_vecstin.uop.exceptionVec(storeAddrMisaligned) && s0_vecActive), false.B) && !s0_misalignWith16Byte 262 263 io.st_mask_out.valid := s0_use_flow_rs || s0_use_flow_vec 264 io.st_mask_out.bits.mask := s0_out.mask 265 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 266 267 io.stin.ready := s1_ready && s0_use_flow_rs 268 io.vecstin.ready := s1_ready && s0_use_flow_vec 269 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 270 io.misalign_stin.ready := s1_ready && s0_use_flow_ma 271 272 // Pipeline 273 // -------------------------------------------------------------------------------- 274 // stage 1 275 // -------------------------------------------------------------------------------- 276 // TLB resp (send paddr to dcache) 277 val s1_valid = RegInit(false.B) 278 val s1_in = RegEnable(s0_out, s0_fire) 279 val s1_out = Wire(new LsPipelineBundle) 280 val s1_kill = Wire(Bool()) 281 val s1_can_go = s2_ready 282 val s1_fire = s1_valid && !s1_kill && s1_can_go 283 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 284 val s1_frm_mabuf = s1_in.isFrmMisAlignBuf 285 val s1_is128bit = s1_in.is128bit 286 287 // mmio cbo decoder 288 val s1_isCbo = RegEnable(s0_isCbo, s0_fire) 289 val s1_vaNeedExt = io.tlb.resp.bits.excp(0).vaNeedExt 290 val s1_isHyper = io.tlb.resp.bits.excp(0).isHyper 291 val s1_paddr = io.tlb.resp.bits.paddr(0) 292 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 293 val s1_fullva = io.tlb.resp.bits.fullva 294 val s1_isForVSnonLeafPTE = io.tlb.resp.bits.isForVSnonLeafPTE 295 val s1_tlb_miss = io.tlb.resp.bits.miss && io.tlb.resp.valid && s1_valid 296 val s1_pbmt = Mux(!s1_tlb_miss, io.tlb.resp.bits.pbmt.head, 0.U(Pbmt.width.W)) 297 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 298 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 299 //We don't want `StoreUnit` to have an additional effect on the Store of vector from a `misalignBuffer,` 300 //But there are places where a marker bit is needed to enable additional processing of vector instructions. 301 //For example: `StoreQueue` is exceptionBuffer 302 val s1_frm_mab_vec = RegEnable(s0_use_flow_ma && io.misalign_stin.bits.isvec, false.B, s0_fire) 303 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 304 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || (s1_tlb_miss && !s1_isvec && !s1_frm_mabuf) 305 306 s1_ready := !s1_valid || s1_kill || s2_ready 307 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 308 when (s0_fire) { s1_valid := true.B } 309 .elsewhen (s1_fire) { s1_valid := false.B } 310 .elsewhen (s1_kill) { s1_valid := false.B } 311 312 // st-ld violation dectect request. 313 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 314 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 315 io.stld_nuke_query.bits.paddr := s1_paddr 316 io.stld_nuke_query.bits.mask := s1_in.mask 317 io.stld_nuke_query.bits.matchLine := (s1_in.isvec || s1_in.misalignWith16Byte) && s1_in.is128bit 318 319 // issue 320 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec && !s1_frm_mabuf 321 io.issue.bits := RegEnable(s0_stin, s0_valid) 322 323 // trigger 324 val storeTrigger = Module(new MemTrigger(MemType.STORE)) 325 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 326 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 327 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 328 storeTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 329 storeTrigger.io.fromLoadStore.vaddr := s1_in.vaddr 330 storeTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 331 storeTrigger.io.fromLoadStore.mask := s1_in.mask 332 storeTrigger.io.isCbo.get := s1_isCbo 333 334 val s1_trigger_action = storeTrigger.io.toLoadStore.triggerAction 335 val s1_trigger_debug_mode = TriggerAction.isDmode(s1_trigger_action) 336 val s1_trigger_breakpoint = TriggerAction.isExp(s1_trigger_action) 337 338 // for misalign in vsMergeBuffer 339 io.s0_s1_valid := s0_valid || s1_valid 340 341 // Send TLB feedback to store issue queue 342 // Store feedback is generated in store_s1, sent to RS in store_s2 343 val s1_feedback = Wire(Valid(new RSFeedback)) 344 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 345 s1_feedback.bits.hit := !s1_tlb_miss 346 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 347 s1_feedback.bits.robIdx := s1_out.uop.robIdx 348 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 349 s1_feedback.bits.dataInvalidSqIdx := DontCare 350 s1_feedback.bits.sqIdx := s1_out.uop.sqIdx 351 s1_feedback.bits.lqIdx := s1_out.uop.lqIdx 352 353 XSDebug(s1_feedback.valid, 354 "S1 Store: tlbHit: %d robIdx: %d\n", 355 s1_feedback.bits.hit, 356 s1_feedback.bits.robIdx.value 357 ) 358 359 // io.feedback_slow := s1_feedback 360 361 // get paddr from dtlb, check if rollback is needed 362 // writeback store inst to lsq 363 s1_out := s1_in 364 s1_out.paddr := s1_paddr 365 s1_out.gpaddr := s1_gpaddr 366 s1_out.fullva := s1_fullva 367 s1_out.vaNeedExt := s1_vaNeedExt 368 s1_out.isHyper := s1_isHyper 369 s1_out.miss := false.B 370 s1_out.nc := Pbmt.isNC(s1_pbmt) 371 s1_out.mmio := Pbmt.isIO(s1_pbmt) 372 s1_out.tlbMiss := s1_tlb_miss 373 s1_out.atomic := Pbmt.isIO(s1_pbmt) 374 s1_out.isForVSnonLeafPTE := s1_isForVSnonLeafPTE 375 when (RegNext(io.tlb.req.bits.checkfullva) && 376 (s1_out.uop.exceptionVec(storePageFault) || 377 s1_out.uop.exceptionVec(storeAccessFault) || 378 s1_out.uop.exceptionVec(storeGuestPageFault))) { 379 s1_out.uop.exceptionVec(storeAddrMisaligned) := false.B 380 } 381 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 382 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 383 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st && s1_vecActive 384 385 s1_out.uop.flushPipe := false.B 386 s1_out.uop.trigger := s1_trigger_action 387 s1_out.uop.exceptionVec(breakPoint) := s1_trigger_breakpoint 388 s1_out.uop.exceptionVec(storeAddrMisaligned) := s1_out.mmio && s1_in.isMisalign 389 s1_out.vecVaddrOffset := Mux( 390 s1_trigger_debug_mode || s1_trigger_breakpoint, 391 storeTrigger.io.toLoadStore.triggerVaddr - s1_in.vecBaseVaddr, 392 s1_in.vaddr + genVFirstUnmask(s1_in.mask).asUInt - s1_in.vecBaseVaddr , 393 ) 394 s1_out.vecTriggerMask := Mux(s1_trigger_debug_mode || s1_trigger_breakpoint, storeTrigger.io.toLoadStore.triggerMask, 0.U) 395 396 // scalar store and scalar load nuke check, and also other purposes 397 //A 128-bit aligned unaligned memory access requires changing the unaligned flag bit in sq 398 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 399 io.lsq.bits := s1_out 400 io.lsq.bits.miss := s1_tlb_miss 401 io.lsq.bits.isvec := s1_out.isvec || s1_frm_mab_vec 402 io.lsq.bits.updateAddrValid := (!s1_in.isMisalign || s1_in.misalignWith16Byte) && (!s1_frm_mabuf || s1_in.isFinalSplit) || s1_exception 403 // kill dcache write intent request when tlb miss or exception 404 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_out.mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 405 io.dcache.s1_paddr := s1_paddr 406 407 // write below io.out.bits assign sentence to prevent overwriting values 408 val s1_tlb_memidx = io.tlb.resp.bits.memidx 409 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 410 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 411 s1_out.uop.debugInfo.tlbRespTime := GTimer() 412 } 413 val s1_mis_align = s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isCbo && !s1_out.nc && !s1_out.mmio && 414 GatedValidRegNext(io.csrCtrl.hd_misalign_st_enable) && s1_in.isMisalign && !s1_in.misalignWith16Byte && 415 !s1_trigger_breakpoint && !s1_trigger_debug_mode 416 417 // Pipeline 418 // -------------------------------------------------------------------------------- 419 // stage 2 420 // -------------------------------------------------------------------------------- 421 // mmio check 422 val s2_valid = RegInit(false.B) 423 val s2_in = RegEnable(s1_out, s1_fire) 424 val s2_out = Wire(new LsPipelineBundle) 425 val s2_kill = Wire(Bool()) 426 val s2_can_go = s3_ready 427 val s2_fire = s2_valid && !s2_kill && s2_can_go 428 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 429 val s2_frm_mabuf = s2_in.isFrmMisAlignBuf 430 val s2_frm_mab_vec = RegEnable(s1_frm_mab_vec, true.B, s1_fire) 431 val s2_pbmt = RegEnable(s1_pbmt, s1_fire) 432 val s2_trigger_debug_mode = RegEnable(s1_trigger_debug_mode, false.B, s1_fire) 433 434 s2_ready := !s2_valid || s2_kill || s3_ready 435 when (s1_fire) { s2_valid := true.B } 436 .elsewhen (s2_fire) { s2_valid := false.B } 437 .elsewhen (s2_kill) { s2_valid := false.B } 438 439 val s2_pmp = WireInit(io.pmp) 440 441 val s2_exception = RegNext(s1_feedback.bits.hit) && 442 (s2_trigger_debug_mode || ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR) && s2_vecActive 443 val s2_un_misalign_exception = RegNext(s1_feedback.bits.hit) && 444 (s2_trigger_debug_mode || ExceptionNO.selectByFuAndUnSelect(s2_out.uop.exceptionVec, StaCfg, Seq(storeAddrMisaligned)).asUInt.orR) 445 446 val s2_mmio = (s2_in.mmio || (Pbmt.isPMA(s2_pbmt) && s2_pmp.mmio)) && RegNext(s1_feedback.bits.hit) 447 val s2_memBackTypeMM = !s2_pmp.mmio 448 val s2_actually_uncache = (Pbmt.isPMA(s2_pbmt) && s2_pmp.mmio || s2_in.nc || s2_in.mmio) && RegNext(s1_feedback.bits.hit) 449 val s2_uncache = !s2_exception && !s2_in.tlbMiss && s2_actually_uncache 450 val s2_isCbo = RegEnable(s1_isCbo, s1_fire) // all cbo instr 451 val s2_isCbo_noZero = LSUOpType.isCbo(s2_in.uop.fuOpType) 452 453 s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec && !s2_frm_mabuf) || s2_in.uop.robIdx.needFlush(io.redirect) 454 455 s2_out := s2_in 456 s2_out.af := s2_out.uop.exceptionVec(storeAccessFault) 457 s2_out.mmio := s2_mmio && !s2_exception 458 s2_out.atomic := s2_in.atomic || Pbmt.isPMA(s2_pbmt) && s2_pmp.atomic 459 s2_out.memBackTypeMM := s2_memBackTypeMM 460 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || 461 s2_pmp.st || 462 ((s2_in.isvec || s2_frm_mabuf || s2_isCbo) && s2_actually_uncache && RegNext(s1_feedback.bits.hit)) 463 ) && s2_vecActive 464 s2_out.uop.exceptionVec(storeAddrMisaligned) := s2_mmio && s2_in.isMisalign && !s2_un_misalign_exception 465 s2_out.uop.vpu.vstart := s2_in.vecVaddrOffset >> s2_in.uop.vpu.veew 466 467 // kill dcache write intent request when mmio or exception 468 io.dcache.s2_kill := (s2_uncache || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 469 io.dcache.s2_pc := s2_out.uop.pc 470 // TODO: dcache resp 471 io.dcache.resp.ready := true.B 472 473 val s2_mis_align = s2_valid && RegEnable(s1_mis_align, s1_fire) && !s2_exception 474 // goto misalignBuffer 475 val toMisalignBufferValid = s2_valid && GatedValidRegNext(s1_mis_align && !s1_frm_mabuf) 476 io.misalign_buf.valid := toMisalignBufferValid 477 io.misalign_buf.bits := s2_in 478 io.misalign_buf.bits.hasException := s2_exception 479 val misalignBufferNack = toMisalignBufferValid && !io.misalign_buf.ready 480 481 // feedback tlb miss to RS in store_s2 482 val feedback_slow_valid = WireInit(false.B) 483 484 feedback_slow_valid := s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect) && !s1_out.isvec && !s1_frm_mabuf 485 io.feedback_slow.valid := GatedValidRegNext(feedback_slow_valid) 486 io.feedback_slow.bits := RegEnable(s1_feedback.bits, feedback_slow_valid) 487 io.feedback_slow.bits.hit := RegEnable(s1_feedback.bits.hit, feedback_slow_valid) && !misalignBufferNack 488 489 val s2_vecFeedback = RegNext(!s1_out.uop.robIdx.needFlush(io.redirect) && s1_feedback.bits.hit && s1_feedback.valid) && 490 !misalignBufferNack && s2_in.isvec && !s2_frm_mabuf 491 492 val s2_misalign_stout = WireInit(0.U.asTypeOf(io.misalign_stout)) 493 s2_misalign_stout.valid := s2_valid && s2_can_go && s2_frm_mabuf 494 connectSamePort(s2_misalign_stout.bits, s2_out) 495 s2_misalign_stout.bits.need_rep := RegEnable(s1_tlb_miss, s1_fire) 496 io.misalign_stout := s2_misalign_stout 497 498 // mmio and exception 499 io.lsq_replenish := s2_out 500 io.lsq_replenish.af := s2_out.af && s2_valid && !s2_kill 501 io.lsq_replenish.mmio := (s2_mmio || s2_isCbo_noZero) && !s2_exception // reuse `mmiostall` logic in sq 502 503 // prefetch related 504 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 505 io.lsq_replenish.updateAddrValid := !s2_mis_align && (!s2_frm_mabuf || s2_out.isFinalSplit) || s2_exception 506 io.lsq_replenish.isvec := s2_out.isvec || s2_frm_mab_vec 507 508 io.lsq_replenish.hasException := (ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR || 509 TriggerAction.isDmode(s2_out.uop.trigger) || s2_out.af) && s2_valid && !s2_kill 510 511 512 // RegNext prefetch train for better timing 513 // ** Now, prefetch train is valid at store s3 ** 514 val s2_prefetch_train_valid = WireInit(false.B) 515 s2_prefetch_train_valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_out.nc && !s2_in.tlbMiss && !s2_in.isHWPrefetch 516 if(EnableStorePrefetchSMS) { 517 io.s1_prefetch_spec := s1_fire 518 io.s2_prefetch_spec := s2_prefetch_train_valid 519 io.prefetch_train.valid := RegNext(s2_prefetch_train_valid) 520 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = s2_prefetch_train_valid) 521 }else { 522 io.s1_prefetch_spec := false.B 523 io.s2_prefetch_spec := false.B 524 io.prefetch_train.valid := false.B 525 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = false.B) 526 } 527 // override miss bit 528 io.prefetch_train.bits.miss := RegEnable(io.dcache.resp.bits.miss, s2_prefetch_train_valid) 529 // TODO: add prefetch and access bit 530 io.prefetch_train.bits.meta_prefetch := false.B 531 io.prefetch_train.bits.meta_access := false.B 532 io.prefetch_train.bits.isFinalSplit := false.B 533 io.prefetch_train.bits.misalignWith16Byte := false.B 534 io.prefetch_train.bits.isMisalign := false.B 535 io.prefetch_train.bits.misalignNeedWakeUp := false.B 536 io.prefetch_train.bits.updateAddrValid := false.B 537 io.prefetch_train.bits.hasException := false.B 538 539 // Pipeline 540 // -------------------------------------------------------------------------------- 541 // stage 3 542 // -------------------------------------------------------------------------------- 543 // store write back 544 val s3_valid = RegInit(false.B) 545 val s3_in = RegEnable(s2_out, s2_fire) 546 val s3_out = Wire(new MemExuOutput(isVector = true)) 547 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 548 val s3_can_go = s3_ready 549 val s3_fire = s3_valid && !s3_kill && s3_can_go 550 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 551 val s3_exception = RegEnable(s2_exception, s2_fire) 552 553 // store misalign will not writeback to rob now 554 when (s2_fire) { s3_valid := (!s2_mmio && !s2_isCbo || s2_exception) && !s2_out.isHWPrefetch && !s2_mis_align && !s2_frm_mabuf } 555 .elsewhen (s3_fire) { s3_valid := false.B } 556 .elsewhen (s3_kill) { s3_valid := false.B } 557 558 // wb: writeback 559 val SelectGroupSize = RollbackGroupSize 560 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 561 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 562 563 s3_out := DontCare 564 s3_out.uop := s3_in.uop 565 s3_out.data := DontCare 566 s3_out.debug.isMMIO := s3_in.mmio 567 s3_out.debug.isNC := s3_in.nc 568 s3_out.debug.paddr := s3_in.paddr 569 s3_out.debug.vaddr := s3_in.vaddr 570 s3_out.debug.isPerfCnt := false.B 571 572 XSError(s3_valid && s3_in.isvec && s3_in.vecActive && !s3_in.mask.orR, "In vecActive, mask complement should not be 0") 573 // Pipeline 574 // -------------------------------------------------------------------------------- 575 // stage x 576 // -------------------------------------------------------------------------------- 577 // delay TotalSelectCycles - 2 cycle(s) 578 val TotalDelayCycles = TotalSelectCycles - 2 579 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 580 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 581 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 582 val sx_in_vec = Wire(Vec(TotalDelayCycles +1, Bool())) 583 584 // backward ready signal 585 s3_ready := sx_ready.head 586 for (i <- 0 until TotalDelayCycles + 1) { 587 if (i == 0) { 588 sx_valid(i) := s3_valid 589 sx_in(i).output := s3_out 590 sx_in(i).vecFeedback := s3_vecFeedback 591 sx_in(i).nc := s3_in.nc 592 sx_in(i).mmio := s3_in.mmio 593 sx_in(i).usSecondInv := s3_in.usSecondInv 594 sx_in(i).elemIdx := s3_in.elemIdx 595 sx_in(i).alignedType := s3_in.alignedType 596 sx_in(i).mbIndex := s3_in.mbIndex 597 sx_in(i).mask := s3_in.mask 598 sx_in(i).vaddr := s3_in.fullva 599 sx_in(i).vaNeedExt := s3_in.vaNeedExt 600 sx_in(i).gpaddr := s3_in.gpaddr 601 sx_in(i).isForVSnonLeafPTE := s3_in.isForVSnonLeafPTE 602 sx_in(i).vecTriggerMask := s3_in.vecTriggerMask 603 sx_in(i).hasException := s3_exception 604 sx_in_vec(i) := s3_in.isvec 605 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 606 } else { 607 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 608 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 609 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 610 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 611 612 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 613 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 614 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 615 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 616 sx_in_vec(i) := RegEnable(sx_in_vec(i-1), prev_fire) 617 } 618 } 619 val sx_last_valid = sx_valid.takeRight(1).head 620 val sx_last_ready = sx_ready.takeRight(1).head 621 val sx_last_in = sx_in.takeRight(1).head 622 val sx_last_in_vec = sx_in_vec.takeRight(1).head 623 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 624 625 // write back: normal store, nc store 626 io.stout.valid := sx_last_valid && !sx_last_in_vec //isStore(sx_last_in.output.uop.fuType) 627 io.stout.bits := sx_last_in.output 628 io.stout.bits.uop.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, StaCfg) 629 630 io.vecstout.valid := sx_last_valid && sx_last_in_vec //isVStore(sx_last_in.output.uop.fuType) 631 // TODO: implement it! 632 io.vecstout.bits.mBIndex := sx_last_in.mbIndex 633 io.vecstout.bits.hit := sx_last_in.vecFeedback 634 io.vecstout.bits.isvec := true.B 635 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 636 io.vecstout.bits.flushState := DontCare 637 io.vecstout.bits.trigger := sx_last_in.output.uop.trigger 638 io.vecstout.bits.nc := sx_last_in.nc 639 io.vecstout.bits.mmio := sx_last_in.mmio 640 io.vecstout.bits.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, VstuCfg) 641 io.vecstout.bits.hasException := sx_last_in.hasException 642 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 643 io.vecstout.bits.vecFeedback := sx_last_in.vecFeedback 644 io.vecstout.bits.elemIdx := sx_last_in.elemIdx 645 io.vecstout.bits.alignedType := sx_last_in.alignedType 646 io.vecstout.bits.mask := sx_last_in.mask 647 io.vecstout.bits.vaddr := sx_last_in.vaddr 648 io.vecstout.bits.vaNeedExt := sx_last_in.vaNeedExt 649 io.vecstout.bits.gpaddr := sx_last_in.gpaddr 650 io.vecstout.bits.isForVSnonLeafPTE := sx_last_in.isForVSnonLeafPTE 651 io.vecstout.bits.vstart := sx_last_in.output.uop.vpu.vstart 652 io.vecstout.bits.vecTriggerMask := sx_last_in.vecTriggerMask 653 // io.vecstout.bits.reg_offset.map(_ := DontCare) 654 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 655 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 656 // io.vecstout.bits.vecdata.map(_ := DontCare) 657 // io.vecstout.bits.mask.map(_ := DontCare) 658 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 659 660 io.debug_ls := DontCare 661 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 662 io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 663 664 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 665 XSDebug(cond, 666 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 667 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 668 p"op ${Binary(pipeline.uop.fuOpType)} " + 669 p"data ${Hexadecimal(pipeline.data)} " + 670 p"mask ${Hexadecimal(pipeline.mask)}\n" 671 ) 672 } 673 674 printPipeLine(s0_out, s0_valid, "S0") 675 printPipeLine(s1_out, s1_valid, "S1") 676 677 // perf cnt 678 XSPerfAccumulate("s0_in_valid", s0_valid) 679 XSPerfAccumulate("s0_in_fire", s0_fire) 680 XSPerfAccumulate("s0_vecin_fire", s0_fire && s0_use_flow_vec) 681 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 682 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 683 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 684 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 685 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 686 687 XSPerfAccumulate("s1_in_valid", s1_valid) 688 XSPerfAccumulate("s1_in_fire", s1_fire) 689 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 690 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 691 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 692 // end 693} 694