1package xiangshan.mem 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.backend.decode.ImmUnion 9import xiangshan.cache._ 10 11// Store Pipeline Stage 0 12// Generate addr, use addr to query DCache and DTLB 13class StoreUnit_S0(implicit p: Parameters) extends XSModule { 14 val io = IO(new Bundle() { 15 val in = Flipped(Decoupled(new ExuInput)) 16 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 17 val isFirstIssue = Input(Bool()) 18 val out = Decoupled(new LsPipelineBundle) 19 val dtlbReq = DecoupledIO(new TlbReq) 20 }) 21 22 // send req to dtlb 23 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 24 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 25 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 26 val saddr_hi = Mux(saddr_lo(12), 27 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 28 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 29 ) 30 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 31 32 io.dtlbReq.bits.vaddr := saddr 33 io.dtlbReq.valid := io.in.valid 34 io.dtlbReq.bits.cmd := TlbCmd.write 35 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 36 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 37 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 38 39 io.out.bits := DontCare 40 io.out.bits.vaddr := saddr 41 42 // Now data use its own io 43 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 44 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 45 io.out.bits.uop := io.in.bits.uop 46 io.out.bits.miss := DontCare 47 io.out.bits.rsIdx := io.rsIdx 48 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 49 io.out.valid := io.in.valid 50 io.in.ready := io.out.ready 51 52 // exception check 53 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 54 "b00".U -> true.B, //b 55 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 56 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 57 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 58 )) 59 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 60 61 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 62 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 63 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 64 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 65} 66 67// Load Pipeline Stage 1 68// TLB resp (send paddr to dcache) 69class StoreUnit_S1(implicit p: Parameters) extends XSModule { 70 val io = IO(new Bundle() { 71 val in = Flipped(Decoupled(new LsPipelineBundle)) 72 val out = Decoupled(new LsPipelineBundle) 73 val lsq = ValidIO(new LsPipelineBundle) 74 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 75 val rsFeedback = ValidIO(new RSFeedback) 76 }) 77 78 val s1_paddr = io.dtlbResp.bits.paddr 79 val s1_tlb_miss = io.dtlbResp.bits.miss 80 val s1_mmio = io.dtlbResp.bits.mmio 81 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 82 83 io.in.ready := true.B 84 85 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 86 87 // Send TLB feedback to store issue queue 88 io.rsFeedback.valid := io.in.valid 89 io.rsFeedback.bits.hit := !s1_tlb_miss 90 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 91 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 92 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 93 XSDebug(io.rsFeedback.valid, 94 "S1 Store: tlbHit: %d roqIdx: %d\n", 95 io.rsFeedback.bits.hit, 96 io.rsFeedback.bits.rsIdx 97 ) 98 99 100 // get paddr from dtlb, check if rollback is needed 101 // writeback store inst to lsq 102 io.lsq.valid := io.in.valid && !s1_tlb_miss 103 io.lsq.bits := io.in.bits 104 io.lsq.bits.paddr := s1_paddr 105 io.lsq.bits.miss := false.B 106 io.lsq.bits.mmio := s1_mmio && !s1_exception 107 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 108 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 109 110 // mmio inst with exception will be writebacked immediately 111 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 112 io.out.bits := io.lsq.bits 113} 114 115class StoreUnit_S2(implicit p: Parameters) extends XSModule { 116 val io = IO(new Bundle() { 117 val in = Flipped(Decoupled(new LsPipelineBundle)) 118 val out = Decoupled(new LsPipelineBundle) 119 }) 120 121 io.in.ready := true.B 122 io.out.bits := io.in.bits 123 io.out.valid := io.in.valid 124 125} 126 127class StoreUnit_S3(implicit p: Parameters) extends XSModule { 128 val io = IO(new Bundle() { 129 val in = Flipped(Decoupled(new LsPipelineBundle)) 130 val stout = DecoupledIO(new ExuOutput) // writeback store 131 }) 132 133 io.in.ready := true.B 134 135 io.stout.valid := io.in.valid 136 io.stout.bits.uop := io.in.bits.uop 137 io.stout.bits.data := DontCare 138 io.stout.bits.redirectValid := false.B 139 io.stout.bits.redirect := DontCare 140 io.stout.bits.debug.isMMIO := io.in.bits.mmio 141 io.stout.bits.debug.paddr := DontCare 142 io.stout.bits.debug.isPerfCnt := false.B 143 io.stout.bits.fflags := DontCare 144 145} 146 147class StoreUnit(implicit p: Parameters) extends XSModule { 148 val io = IO(new Bundle() { 149 val stin = Flipped(Decoupled(new ExuInput)) 150 val redirect = Flipped(ValidIO(new Redirect)) 151 val flush = Input(Bool()) 152 val rsFeedback = ValidIO(new RSFeedback) 153 val dtlb = new TlbRequestIO() 154 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 155 val isFirstIssue = Input(Bool()) 156 val lsq = ValidIO(new LsPipelineBundle) 157 val stout = DecoupledIO(new ExuOutput) // writeback store 158 }) 159 160 val store_s0 = Module(new StoreUnit_S0) 161 val store_s1 = Module(new StoreUnit_S1) 162 val store_s2 = Module(new StoreUnit_S2) 163 val store_s3 = Module(new StoreUnit_S3) 164 165 store_s0.io.in <> io.stin 166 store_s0.io.dtlbReq <> io.dtlb.req 167 store_s0.io.rsIdx := io.rsIdx 168 store_s0.io.isFirstIssue := io.isFirstIssue 169 170 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 171 172 store_s1.io.lsq <> io.lsq // send result to sq 173 store_s1.io.dtlbResp <> io.dtlb.resp 174 store_s1.io.rsFeedback <> io.rsFeedback 175 176 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 177 178 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 179 180 store_s3.io.stout <> io.stout 181 182 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 183 XSDebug(cond, 184 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 185 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 186 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 187 p"data ${Hexadecimal(pipeline.data)} " + 188 p"mask ${Hexadecimal(pipeline.mask)}\n" 189 ) 190 } 191 192 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 193 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 194 195} 196