1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TLB, TlbCmd, TlbPtwIO, TlbReq, TlbRequestIO, TlbResp} 28 29// Store Pipeline Stage 0 30// Generate addr, use addr to query DCache and DTLB 31class StoreUnit_S0(implicit p: Parameters) extends XSModule { 32 val io = IO(new Bundle() { 33 val in = Flipped(Decoupled(new ExuInput)) 34 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 35 val isFirstIssue = Input(Bool()) 36 val out = Decoupled(new LsPipelineBundle) 37 val dtlbReq = DecoupledIO(new TlbReq) 38 }) 39 40 // send req to dtlb 41 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 42 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 43 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 44 val saddr_hi = Mux(saddr_lo(12), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 46 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 47 ) 48 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 49 50 io.dtlbReq.bits.vaddr := saddr 51 io.dtlbReq.valid := io.in.valid 52 io.dtlbReq.bits.cmd := TlbCmd.write 53 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 54 io.dtlbReq.bits.robIdx := io.in.bits.uop.robIdx 55 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 56 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 57 58 io.out.bits := DontCare 59 io.out.bits.vaddr := saddr 60 61 // Now data use its own io 62 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 63 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 64 io.out.bits.uop := io.in.bits.uop 65 io.out.bits.miss := DontCare 66 io.out.bits.rsIdx := io.rsIdx 67 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 68 io.out.bits.isFirstIssue := io.isFirstIssue 69 io.out.bits.wlineflag := io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_zero 70 io.out.valid := io.in.valid 71 io.in.ready := io.out.ready 72 73 // exception check 74 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 75 "b00".U -> true.B, //b 76 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 77 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 78 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 79 )) 80 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 81 82 XSPerfAccumulate("in_valid", io.in.valid) 83 XSPerfAccumulate("in_fire", io.in.fire) 84 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.isFirstIssue) 85 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 86 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 87 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 88 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 89} 90 91// Store Pipeline Stage 1 92// TLB resp (send paddr to dcache) 93class StoreUnit_S1(implicit p: Parameters) extends XSModule { 94 val io = IO(new Bundle() { 95 val in = Flipped(Decoupled(new LsPipelineBundle)) 96 val out = Decoupled(new LsPipelineBundle) 97 val lsq = ValidIO(new LsPipelineBundle) 98 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 99 val rsFeedback = ValidIO(new RSFeedback) 100 }) 101 102 // mmio cbo decoder 103 val is_mmio_cbo = io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 104 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 105 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_inval 106 107 val s1_paddr = io.dtlbResp.bits.paddr 108 val s1_tlb_miss = io.dtlbResp.bits.miss 109 val s1_mmio = io.dtlbResp.bits.mmio || is_mmio_cbo 110 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 111 112 io.in.ready := true.B 113 114 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 115 116 // Send TLB feedback to store issue queue 117 io.rsFeedback.valid := io.in.valid 118 io.rsFeedback.bits.hit := !s1_tlb_miss 119 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 120 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 121 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 122 XSDebug(io.rsFeedback.valid, 123 "S1 Store: tlbHit: %d robIdx: %d\n", 124 io.rsFeedback.bits.hit, 125 io.rsFeedback.bits.rsIdx 126 ) 127 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 128 129 // get paddr from dtlb, check if rollback is needed 130 // writeback store inst to lsq 131 io.lsq.valid := io.in.valid && !s1_tlb_miss 132 io.lsq.bits := io.in.bits 133 io.lsq.bits.paddr := s1_paddr 134 io.lsq.bits.miss := false.B 135 io.lsq.bits.mmio := s1_mmio && !s1_exception 136 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 137 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 138 139 // mmio inst with exception will be writebacked immediately 140 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 141 io.out.bits := io.lsq.bits 142 143 XSPerfAccumulate("in_valid", io.in.valid) 144 XSPerfAccumulate("in_fire", io.in.fire) 145 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 146 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 147 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 148} 149 150class StoreUnit_S2(implicit p: Parameters) extends XSModule { 151 val io = IO(new Bundle() { 152 val in = Flipped(Decoupled(new LsPipelineBundle)) 153 val pmpResp = Input(new PMPRespBundle) 154 val out = Decoupled(new LsPipelineBundle) 155 }) 156 157 io.in.ready := true.B 158 io.out.bits := io.in.bits 159 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.in.bits.uop.cf.exceptionVec(storeAccessFault) || io.pmpResp.st 160 io.out.valid := io.in.valid 161 162} 163 164class StoreUnit_S3(implicit p: Parameters) extends XSModule { 165 val io = IO(new Bundle() { 166 val in = Flipped(Decoupled(new LsPipelineBundle)) 167 val stout = DecoupledIO(new ExuOutput) // writeback store 168 }) 169 170 io.in.ready := true.B 171 172 io.stout.valid := io.in.valid 173 io.stout.bits.uop := io.in.bits.uop 174 io.stout.bits.data := DontCare 175 io.stout.bits.redirectValid := false.B 176 io.stout.bits.redirect := DontCare 177 io.stout.bits.debug.isMMIO := io.in.bits.mmio 178 io.stout.bits.debug.paddr := DontCare 179 io.stout.bits.debug.isPerfCnt := false.B 180 io.stout.bits.fflags := DontCare 181 182} 183 184class StoreUnit(implicit p: Parameters) extends XSModule { 185 val io = IO(new Bundle() { 186 val stin = Flipped(Decoupled(new ExuInput)) 187 val redirect = Flipped(ValidIO(new Redirect)) 188 val feedbackSlow = ValidIO(new RSFeedback) 189 val tlb = new TlbRequestIO() 190 val pmp = Input(new PMPRespBundle()) 191 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 192 val isFirstIssue = Input(Bool()) 193 val lsq = ValidIO(new LsPipelineBundle) 194 val stout = DecoupledIO(new ExuOutput) // writeback store 195 }) 196 197 val store_s0 = Module(new StoreUnit_S0) 198 val store_s1 = Module(new StoreUnit_S1) 199 val store_s2 = Module(new StoreUnit_S2) 200 val store_s3 = Module(new StoreUnit_S3) 201 202 store_s0.io.in <> io.stin 203 store_s0.io.dtlbReq <> io.tlb.req 204 store_s0.io.rsIdx := io.rsIdx 205 store_s0.io.isFirstIssue := io.isFirstIssue 206 207 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 208 209 store_s1.io.lsq <> io.lsq // send result to sq 210 store_s1.io.dtlbResp <> io.tlb.resp 211 store_s1.io.rsFeedback <> io.feedbackSlow 212 213 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 214 215 store_s2.io.pmpResp <> io.pmp 216 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 217 218 store_s3.io.stout <> io.stout 219 220 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 221 XSDebug(cond, 222 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 223 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 224 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 225 p"data ${Hexadecimal(pipeline.data)} " + 226 p"mask ${Hexadecimal(pipeline.mask)}\n" 227 ) 228 } 229 230 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 231 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 232} 233