1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TLB, TlbCmd, TlbPtwIO, TlbReq, TlbRequestIO, TlbResp} 28 29// Store Pipeline Stage 0 30// Generate addr, use addr to query DCache and DTLB 31class StoreUnit_S0(implicit p: Parameters) extends XSModule { 32 val io = IO(new Bundle() { 33 val in = Flipped(Decoupled(new ExuInput)) 34 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 35 val isFirstIssue = Input(Bool()) 36 val out = Decoupled(new LsPipelineBundle) 37 val dtlbReq = DecoupledIO(new TlbReq) 38 }) 39 40 // send req to dtlb 41 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 42 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 43 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 44 val saddr_hi = Mux(saddr_lo(12), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 46 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 47 ) 48 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 49 50 io.dtlbReq.bits.vaddr := saddr 51 io.dtlbReq.valid := io.in.valid 52 io.dtlbReq.bits.cmd := TlbCmd.write 53 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 54 io.dtlbReq.bits.robIdx := io.in.bits.uop.robIdx 55 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 56 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 57 58 io.out.bits := DontCare 59 io.out.bits.vaddr := saddr 60 61 // Now data use its own io 62 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 63 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 64 io.out.bits.uop := io.in.bits.uop 65 io.out.bits.miss := DontCare 66 io.out.bits.rsIdx := io.rsIdx 67 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 68 io.out.bits.isFirstIssue := io.isFirstIssue 69 io.out.valid := io.in.valid 70 io.in.ready := io.out.ready 71 72 // exception check 73 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 74 "b00".U -> true.B, //b 75 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 76 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 77 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 78 )) 79 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 80 81 XSPerfAccumulate("in_valid", io.in.valid) 82 XSPerfAccumulate("in_fire", io.in.fire) 83 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.isFirstIssue) 84 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 85 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 86 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 87 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 88} 89 90// Store Pipeline Stage 1 91// TLB resp (send paddr to dcache) 92class StoreUnit_S1(implicit p: Parameters) extends XSModule { 93 val io = IO(new Bundle() { 94 val in = Flipped(Decoupled(new LsPipelineBundle)) 95 val out = Decoupled(new LsPipelineBundle) 96 val lsq = ValidIO(new LsPipelineBundle) 97 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 98 val rsFeedback = ValidIO(new RSFeedback) 99 }) 100 101 val s1_paddr = io.dtlbResp.bits.paddr 102 val s1_tlb_miss = io.dtlbResp.bits.miss 103 val s1_mmio = io.dtlbResp.bits.mmio 104 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 105 106 io.in.ready := true.B 107 108 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 109 110 // Send TLB feedback to store issue queue 111 io.rsFeedback.valid := io.in.valid 112 io.rsFeedback.bits.hit := !s1_tlb_miss 113 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 114 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 115 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 116 XSDebug(io.rsFeedback.valid, 117 "S1 Store: tlbHit: %d robIdx: %d\n", 118 io.rsFeedback.bits.hit, 119 io.rsFeedback.bits.rsIdx 120 ) 121 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 122 123 // get paddr from dtlb, check if rollback is needed 124 // writeback store inst to lsq 125 io.lsq.valid := io.in.valid && !s1_tlb_miss 126 io.lsq.bits := io.in.bits 127 io.lsq.bits.paddr := s1_paddr 128 io.lsq.bits.miss := false.B 129 io.lsq.bits.mmio := s1_mmio && !s1_exception 130 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 131 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 132 133 // mmio inst with exception will be writebacked immediately 134 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 135 io.out.bits := io.lsq.bits 136 137 XSPerfAccumulate("in_valid", io.in.valid) 138 XSPerfAccumulate("in_fire", io.in.fire) 139 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 140 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 141 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 142} 143 144class StoreUnit_S2(implicit p: Parameters) extends XSModule { 145 val io = IO(new Bundle() { 146 val in = Flipped(Decoupled(new LsPipelineBundle)) 147 val pmpResp = Input(new PMPRespBundle) 148 val out = Decoupled(new LsPipelineBundle) 149 }) 150 151 io.in.ready := true.B 152 io.out.bits := io.in.bits 153 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.in.bits.uop.cf.exceptionVec(storeAccessFault) || io.pmpResp.st 154 io.out.valid := io.in.valid 155 156} 157 158class StoreUnit_S3(implicit p: Parameters) extends XSModule { 159 val io = IO(new Bundle() { 160 val in = Flipped(Decoupled(new LsPipelineBundle)) 161 val stout = DecoupledIO(new ExuOutput) // writeback store 162 }) 163 164 io.in.ready := true.B 165 166 io.stout.valid := io.in.valid 167 io.stout.bits.uop := io.in.bits.uop 168 io.stout.bits.data := DontCare 169 io.stout.bits.redirectValid := false.B 170 io.stout.bits.redirect := DontCare 171 io.stout.bits.debug.isMMIO := io.in.bits.mmio 172 io.stout.bits.debug.paddr := DontCare 173 io.stout.bits.debug.isPerfCnt := false.B 174 io.stout.bits.fflags := DontCare 175 176} 177 178class StoreUnit(implicit p: Parameters) extends XSModule { 179 val io = IO(new Bundle() { 180 val stin = Flipped(Decoupled(new ExuInput)) 181 val redirect = Flipped(ValidIO(new Redirect)) 182 val flush = Input(Bool()) 183 val feedbackSlow = ValidIO(new RSFeedback) 184 val tlb = new TlbRequestIO() 185 val pmp = Input(new PMPRespBundle()) 186 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 187 val isFirstIssue = Input(Bool()) 188 val lsq = ValidIO(new LsPipelineBundle) 189 val stout = DecoupledIO(new ExuOutput) // writeback store 190 }) 191 192 val store_s0 = Module(new StoreUnit_S0) 193 val store_s1 = Module(new StoreUnit_S1) 194 val store_s2 = Module(new StoreUnit_S2) 195 val store_s3 = Module(new StoreUnit_S3) 196 197 store_s0.io.in <> io.stin 198 store_s0.io.dtlbReq <> io.tlb.req 199 store_s0.io.rsIdx := io.rsIdx 200 store_s0.io.isFirstIssue := io.isFirstIssue 201 202 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect, io.flush)) 203 204 store_s1.io.lsq <> io.lsq // send result to sq 205 store_s1.io.dtlbResp <> io.tlb.resp 206 store_s1.io.rsFeedback <> io.feedbackSlow 207 208 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect, io.flush)) 209 210 store_s2.io.pmpResp <> io.pmp 211 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect, io.flush)) 212 213 store_s3.io.stout <> io.stout 214 215 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 216 XSDebug(cond, 217 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 218 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 219 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 220 p"data ${Hexadecimal(pipeline.data)} " + 221 p"mask ${Hexadecimal(pipeline.mask)}\n" 222 ) 223 } 224 225 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 226 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 227} 228