1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 16 val out = Decoupled(new LsPipelineBundle) 17 val dtlbReq = DecoupledIO(new TlbReq) 18 }) 19 20 // send req to dtlb 21 // val saddr = io.in.bits.src1 + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 22 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 23 val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 24 val saddr_hi = Mux(saddr_lo(12), 25 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U), 26 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)), 27 ) 28 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 29 30 io.dtlbReq.bits.vaddr := saddr 31 io.dtlbReq.valid := io.in.valid 32 io.dtlbReq.bits.cmd := TlbCmd.write 33 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 34 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 35 36 io.out.bits := DontCare 37 io.out.bits.vaddr := saddr 38 39 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 40 io.out.bits.uop := io.in.bits.uop 41 io.out.bits.miss := DontCare 42 io.out.bits.rsIdx := io.rsIdx 43 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 44 io.out.valid := io.in.valid 45 io.in.ready := io.out.ready 46 47 // exception check 48 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 49 "b00".U -> true.B, //b 50 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 51 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 52 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 53 )) 54 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 55 56} 57 58// Load Pipeline Stage 1 59// TLB resp (send paddr to dcache) 60class StoreUnit_S1 extends XSModule { 61 val io = IO(new Bundle() { 62 val in = Flipped(Decoupled(new LsPipelineBundle)) 63 val out = Decoupled(new LsPipelineBundle) 64 val lsq = ValidIO(new LsPipelineBundle) 65 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 66 val tlbFeedback = ValidIO(new TlbFeedback) 67 }) 68 69 val s1_paddr = io.dtlbResp.bits.paddr 70 val s1_tlb_miss = io.dtlbResp.bits.miss 71 val s1_mmio = io.dtlbResp.bits.mmio 72 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 73 74 io.in.ready := true.B 75 76 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 77 78 // Send TLB feedback to store issue queue 79 io.tlbFeedback.valid := io.in.valid 80 io.tlbFeedback.bits.hit := !s1_tlb_miss 81 io.tlbFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 82 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 83 XSDebug(io.tlbFeedback.valid, 84 "S1 Store: tlbHit: %d roqIdx: %d\n", 85 io.tlbFeedback.bits.hit, 86 io.tlbFeedback.bits.rsIdx 87 ) 88 89 90 // get paddr from dtlb, check if rollback is needed 91 // writeback store inst to lsq 92 io.lsq.valid := io.in.valid && !s1_tlb_miss 93 io.lsq.bits := io.in.bits 94 io.lsq.bits.paddr := s1_paddr 95 io.lsq.bits.miss := false.B 96 io.lsq.bits.mmio := s1_mmio && !s1_exception 97 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 98 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 99 100 // mmio inst with exception will be writebacked immediately 101 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 102 io.out.bits := io.lsq.bits 103} 104 105class StoreUnit_S2 extends XSModule { 106 val io = IO(new Bundle() { 107 val in = Flipped(Decoupled(new LsPipelineBundle)) 108 val out = Decoupled(new LsPipelineBundle) 109 }) 110 111 io.in.ready := true.B 112 io.out.bits := io.in.bits 113 io.out.valid := io.in.valid 114 115} 116 117class StoreUnit_S3 extends XSModule { 118 val io = IO(new Bundle() { 119 val in = Flipped(Decoupled(new LsPipelineBundle)) 120 val stout = DecoupledIO(new ExuOutput) // writeback store 121 }) 122 123 io.in.ready := true.B 124 125 io.stout.valid := io.in.valid 126 io.stout.bits.uop := io.in.bits.uop 127 io.stout.bits.data := DontCare 128 io.stout.bits.redirectValid := false.B 129 io.stout.bits.redirect := DontCare 130 io.stout.bits.debug.isMMIO := io.in.bits.mmio 131 io.stout.bits.debug.paddr := DontCare 132 io.stout.bits.debug.isPerfCnt := false.B 133 io.stout.bits.fflags := DontCare 134 135} 136 137class StoreUnit extends XSModule { 138 val io = IO(new Bundle() { 139 val stin = Flipped(Decoupled(new ExuInput)) 140 val redirect = Flipped(ValidIO(new Redirect)) 141 val flush = Input(Bool()) 142 val tlbFeedback = ValidIO(new TlbFeedback) 143 val dtlb = new TlbRequestIO() 144 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 145 val lsq = ValidIO(new LsPipelineBundle) 146 val stout = DecoupledIO(new ExuOutput) // writeback store 147 }) 148 149 val store_s0 = Module(new StoreUnit_S0) 150 val store_s1 = Module(new StoreUnit_S1) 151 val store_s2 = Module(new StoreUnit_S2) 152 val store_s3 = Module(new StoreUnit_S3) 153 154 store_s0.io.in <> io.stin 155 store_s0.io.dtlbReq <> io.dtlb.req 156 store_s0.io.rsIdx := io.rsIdx 157 158 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 159 160 store_s1.io.lsq <> io.lsq // send result to sq 161 store_s1.io.dtlbResp <> io.dtlb.resp 162 store_s1.io.tlbFeedback <> io.tlbFeedback 163 164 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 165 166 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 167 168 store_s3.io.stout <> io.stout 169 170 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 171 XSDebug(cond, 172 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 173 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 174 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 175 p"data ${Hexadecimal(pipeline.data)} " + 176 p"mask ${Hexadecimal(pipeline.mask)}\n" 177 ) 178 } 179 180 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 181 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 182 183} 184