1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.rob.DebugLsInfoBundle 28import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 29import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 30 31class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 32 val io = IO(new Bundle() { 33 val redirect = Flipped(ValidIO(new Redirect)) 34 val stin = Flipped(Decoupled(new ExuInput)) 35 val issue = Valid(new ExuInput) 36 val tlb = new TlbRequestIO() 37 val dcache = new DCacheStoreIO 38 val pmp = Flipped(new PMPRespBundle()) 39 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 40 val isFirstIssue = Input(Bool()) 41 val lsq = ValidIO(new LsPipelineBundle) 42 val lsq_replenish = Output(new LsPipelineBundle()) 43 val feedback_slow = ValidIO(new RSFeedback) 44 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 45 // provide prefetch info to sms 46 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 47 val stld_nuke_query = Valid(new StoreNukeQueryIO) 48 val stout = DecoupledIO(new ExuOutput) // writeback store 49 // store mask, send to sq in store_s0 50 val st_mask_out = Valid(new StoreMaskBundle) 51 val debug_ls = Output(new DebugLsInfoBundle) 52 }) 53 54 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 55 56 // Pipeline 57 // -------------------------------------------------------------------------------- 58 // stage 0 59 // -------------------------------------------------------------------------------- 60 // generate addr, use addr to query DCache and DTLB 61 val s0_iss_valid = io.stin.valid 62 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 63 val s0_valid = s0_iss_valid || s0_prf_valid 64 val s0_use_flow_rs = s0_iss_valid 65 val s0_use_flow_prf = !s0_iss_valid && s0_prf_valid 66 val s0_in = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 67 val s0_isFirstIssue = Mux(s0_use_flow_rs, io.isFirstIssue, false.B) 68 val s0_rsIdx = Mux(s0_use_flow_rs, io.rsIdx, 0.U) 69 val s0_size = Mux(s0_use_flow_rs, LSUOpType.size(s0_in.uop.ctrl.fuOpType), 3.U) 70 val s0_mem_idx = Mux(s0_use_flow_rs, s0_in.uop.sqIdx.value, 0.U) 71 val s0_rob_idx = Mux(s0_use_flow_rs, s0_in.uop.robIdx, 0.U.asTypeOf(s0_in.uop.robIdx)) 72 val s0_pc = Mux(s0_use_flow_rs, s0_in.uop.cf.pc, 0.U) 73 val s0_instr_type = Mux(s0_use_flow_rs, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 74 val s0_wlineflag = Mux(s0_use_flow_rs, s0_in.uop.ctrl.fuOpType === LSUOpType.cbo_zero, false.B) 75 val s0_out = Wire(new LsPipelineBundle) 76 val s0_kill = s0_in.uop.robIdx.needFlush(io.redirect) 77 val s0_can_go = s1_ready 78 val s0_fire = s0_valid && !s0_kill && s0_can_go 79 80 // generate addr 81 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.ctrl.imm(11,0), VAddrBits) 82 val imm12 = WireInit(s0_in.uop.ctrl.imm(11,0)) 83 val saddr_lo = s0_in.src(0)(11,0) + Cat(0.U(1.W), imm12) 84 val saddr_hi = Mux(saddr_lo(12), 85 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12), s0_in.src(0)(VAddrBits-1, 12)+1.U), 86 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_in.src(0)(VAddrBits-1, 12)), 87 ) 88 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 89 val s0_vaddr = Mux(s0_use_flow_rs, s0_saddr, io.prefetch_req.bits.vaddr) 90 val s0_mask = Mux(s0_use_flow_rs, genVWmask(s0_saddr, s0_in.uop.ctrl.fuOpType(1,0)), 3.U) 91 92 io.tlb.req.valid := s0_valid 93 io.tlb.req.bits.vaddr := s0_vaddr 94 io.tlb.req.bits.cmd := TlbCmd.write 95 io.tlb.req.bits.size := s0_size 96 io.tlb.req.bits.kill := false.B 97 io.tlb.req.bits.memidx.is_ld := false.B 98 io.tlb.req.bits.memidx.is_st := true.B 99 io.tlb.req.bits.memidx.idx := s0_mem_idx 100 io.tlb.req.bits.debug.robIdx := s0_rob_idx 101 io.tlb.req.bits.no_translate := false.B 102 io.tlb.req.bits.debug.pc := s0_pc 103 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 104 io.tlb.req_kill := false.B 105 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_in.uop.ctrl.fuOpType) 106 io.tlb.req.bits.hlvx := false.B 107 108 // Dcache access here: not **real** dcache write 109 // just read meta and tag in dcache, to find out the store will hit or miss 110 111 // NOTE: The store request does not wait for the dcache to be ready. 112 // If the dcache is not ready at this time, the dcache is not queried. 113 // But, store prefetch request will always wait for dcache to be ready to make progress. 114 io.dcache.req.valid := s0_fire 115 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 116 io.dcache.req.bits.vaddr := s0_vaddr 117 io.dcache.req.bits.instrtype := s0_instr_type 118 119 s0_out := DontCare 120 s0_out.vaddr := s0_vaddr 121 // Now data use its own io 122 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.ctrl.fuOpType(1,0)) 123 s0_out.data := s0_in.src(1) // FIXME: remove data from pipeline 124 s0_out.uop := s0_in.uop 125 s0_out.miss := false.B 126 s0_out.rsIdx := s0_rsIdx 127 s0_out.mask := s0_mask 128 s0_out.isFirstIssue := s0_isFirstIssue 129 s0_out.isHWPrefetch := s0_use_flow_prf 130 s0_out.wlineflag := s0_wlineflag 131 when(s0_valid && s0_isFirstIssue) { 132 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 133 } 134 135 // exception check 136 val s0_addr_aligned = LookupTree(s0_in.uop.ctrl.fuOpType(1,0), List( 137 "b00".U -> true.B, //b 138 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 139 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 140 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 141 )) 142 s0_out.uop.cf.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs, !s0_addr_aligned, false.B) 143 144 io.st_mask_out.valid := s0_use_flow_rs 145 io.st_mask_out.bits.mask := s0_out.mask 146 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 147 148 io.stin.ready := s1_ready 149 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid 150 151 // Pipeline 152 // -------------------------------------------------------------------------------- 153 // stage 1 154 // -------------------------------------------------------------------------------- 155 // TLB resp (send paddr to dcache) 156 val s1_valid = RegInit(false.B) 157 val s1_in = RegEnable(s0_out, s0_fire) 158 val s1_out = Wire(new LsPipelineBundle) 159 val s1_kill = Wire(Bool()) 160 val s1_can_go = s2_ready 161 val s1_fire = s1_valid && !s1_kill && s1_can_go 162 163 // mmio cbo decoder 164 val s1_mmio_cbo = s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 165 s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 166 s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_inval 167 val s1_paddr = io.tlb.resp.bits.paddr(0) 168 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 169 val s1_tlb_miss = io.tlb.resp.bits.miss 170 val s1_mmio = s1_mmio_cbo 171 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.cf.exceptionVec, staCfg).asUInt.orR 172 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 173 174 s1_ready := !s1_valid || s1_kill || s2_ready 175 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 176 when (s0_fire) { s1_valid := true.B } 177 .elsewhen (s1_fire) { s1_valid := false.B } 178 .elsewhen (s1_kill) { s1_valid := false.B } 179 180 // st-ld violation dectect request. 181 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 182 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 183 io.stld_nuke_query.bits.paddr := s1_paddr 184 io.stld_nuke_query.bits.mask := s1_in.mask 185 186 // issue 187 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 188 io.issue.bits := RegEnable(s0_in, s0_valid) 189 190 191 // Send TLB feedback to store issue queue 192 // Store feedback is generated in store_s1, sent to RS in store_s2 193 val s1_feedback = Wire(Valid(new RSFeedback)) 194 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 195 s1_feedback.bits.hit := !s1_tlb_miss 196 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 197 s1_feedback.bits.rsIdx := s1_out.rsIdx 198 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 199 s1_feedback.bits.dataInvalidSqIdx := DontCare 200 XSDebug(s1_feedback.valid, 201 "S1 Store: tlbHit: %d robIdx: %d\n", 202 s1_feedback.bits.hit, 203 s1_feedback.bits.rsIdx 204 ) 205 206 io.feedback_slow := s1_feedback 207 208 // get paddr from dtlb, check if rollback is needed 209 // writeback store inst to lsq 210 s1_out := s1_in 211 s1_out.paddr := s1_paddr 212 s1_out.gpaddr := s1_gpaddr 213 s1_out.miss := false.B 214 s1_out.mmio := s1_mmio 215 s1_out.tlbMiss := s1_tlb_miss 216 s1_out.atomic := s1_mmio 217 s1_out.uop.cf.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 218 s1_out.uop.cf.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 219 s1_out.uop.cf.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st 220 221 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 222 io.lsq.bits := s1_out 223 io.lsq.bits.miss := s1_tlb_miss 224 225 // kill dcache write intent request when tlb miss or exception 226 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 227 io.dcache.s1_paddr := s1_paddr 228 229 // write below io.out.bits assign sentence to prevent overwriting values 230 val s1_tlb_memidx = io.tlb.resp.bits.memidx 231 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 232 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 233 s1_out.uop.debugInfo.tlbRespTime := GTimer() 234 } 235 236 // Pipeline 237 // -------------------------------------------------------------------------------- 238 // stage 2 239 // -------------------------------------------------------------------------------- 240 // mmio check 241 val s2_valid = RegInit(false.B) 242 val s2_in = RegEnable(s1_out, s1_fire) 243 val s2_out = Wire(new LsPipelineBundle) 244 val s2_kill = Wire(Bool()) 245 val s2_can_go = s3_ready 246 val s2_fire = s2_valid && !s2_kill && s2_can_go 247 248 s2_ready := !s2_valid || s2_kill || s3_ready 249 when (s1_fire) { s2_valid := true.B } 250 .elsewhen (s2_fire) { s2_valid := false.B } 251 .elsewhen (s2_kill) { s2_valid := false.B } 252 253 val s2_pmp = WireInit(io.pmp) 254 255 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.cf.exceptionVec, staCfg).asUInt.orR 256 val s2_mmio = s2_in.mmio || s2_pmp.mmio 257 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 258 259 s2_out := s2_in 260 s2_out.mmio := s2_mmio && !s2_exception 261 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 262 s2_out.uop.cf.exceptionVec(storeAccessFault) := s2_in.uop.cf.exceptionVec(storeAccessFault) || s2_pmp.st 263 264 // kill dcache write intent request when mmio or exception 265 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 266 io.dcache.s2_pc := s2_out.uop.cf.pc 267 // TODO: dcache resp 268 io.dcache.resp.ready := true.B 269 270 // feedback tlb miss to RS in store_s2 271 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 272 io.feedback_slow.bits := RegNext(s1_feedback.bits) 273 274 // mmio and exception 275 io.lsq_replenish := s2_out 276 277 // prefetch related 278 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 279 280 // RegNext prefetch train for better timing 281 // ** Now, prefetch train is valid at store s3 ** 282 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true) 283 // override miss bit 284 io.prefetch_train.bits.miss := RegNext(io.dcache.resp.bits.miss) 285 // TODO: add prefetch and access bit 286 io.prefetch_train.bits.meta_prefetch := false.B 287 io.prefetch_train.bits.meta_access := false.B 288 if(EnableStorePrefetchSMS) { 289 io.prefetch_train.valid := RegNext(s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch) 290 }else { 291 io.prefetch_train.valid := false.B 292 } 293 294 // Pipeline 295 // -------------------------------------------------------------------------------- 296 // stage 3 297 // -------------------------------------------------------------------------------- 298 // store write back 299 val s3_valid = RegInit(false.B) 300 val s3_in = RegEnable(s2_out, s2_fire) 301 val s3_out = Wire(new ExuOutput) 302 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 303 val s3_can_go = s3_ready 304 val s3_fire = s3_valid && !s3_kill && s3_can_go 305 306 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 307 .elsewhen (s3_fire) { s3_valid := false.B } 308 .elsewhen (s3_kill) { s3_valid := false.B } 309 310 // wb: writeback 311 val SelectGroupSize = RollbackGroupSize 312 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 313 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 314 315 s3_out := DontCare 316 s3_out.uop := s3_in.uop 317 s3_out.data := DontCare 318 s3_out.redirectValid := false.B 319 s3_out.redirect := DontCare 320 s3_out.debug.isMMIO := s3_in.mmio 321 s3_out.debug.paddr := s3_in.paddr 322 s3_out.debug.vaddr := s3_in.vaddr 323 s3_out.debug.isPerfCnt := false.B 324 s3_out.fflags := DontCare 325 326 // Pipeline 327 // -------------------------------------------------------------------------------- 328 // stage x 329 // -------------------------------------------------------------------------------- 330 // delay TotalSelectCycles - 2 cycle(s) 331 val TotalDelayCycles = TotalSelectCycles - 2 332 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 333 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 334 val sx_in = Wire(Vec(TotalDelayCycles + 1, new ExuOutput)) 335 336 // backward ready signal 337 s3_ready := sx_ready.head 338 for (i <- 0 until TotalDelayCycles + 1) { 339 if (i == 0) { 340 sx_valid(i) := s3_valid 341 sx_in(i) := s3_out 342 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 343 } else { 344 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 345 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 346 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 347 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 348 349 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 350 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 351 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 352 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 353 } 354 } 355 val sx_last_valid = sx_valid.takeRight(1).head 356 val sx_last_ready = sx_ready.takeRight(1).head 357 val sx_last_in = sx_in.takeRight(1).head 358 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 359 360 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) 361 io.stout.bits := sx_last_in 362 io.stout.bits.redirectValid := false.B 363 364 io.debug_ls := DontCare 365 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 366 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 367 368 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 369 XSDebug(cond, 370 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 371 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 372 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 373 p"data ${Hexadecimal(pipeline.data)} " + 374 p"mask ${Hexadecimal(pipeline.mask)}\n" 375 ) 376 } 377 378 printPipeLine(s0_out, s0_valid, "S0") 379 printPipeLine(s1_out, s1_valid, "S1") 380 381 // perf cnt 382 XSPerfAccumulate("s0_in_valid", s0_valid) 383 XSPerfAccumulate("s0_in_fire", s0_fire) 384 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 385 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12)) 386 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12)) 387 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 388 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 389 390 XSPerfAccumulate("s1_in_valid", s1_valid) 391 XSPerfAccumulate("s1_in_fire", s1_fire) 392 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 393 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 394 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 395 // end 396}